entity lcd16x2 isport(Clk : in std_logic; -- system clock(5MHz) Rst : in std_logic; -- asynchronous reset, active high Tick : in std_logic; -- 250KHz(4us) pulse train, 펄스폭:clk 한주기 Din : in std_Logic_vector(23 downto 0); -- input data packet Wstrb : in std_Logic; -- write data strobe, 펄스폭:clk 한주기, active high Busy : out std_Logic; -- device busy, active high -- LCD interface signals Dout : inout std_Logic_vector(3 downto 0); -- 4 bit mode Rs : out std_Logic; -- command(‘0’)/data(‘1’) select Rw : out std_Logic; -- LCD Read(‘1’)/nWrite(‘0’), always `0`(write) En : out std_Logic -- LCD Enable, active high);end lcd16x2;
16x2 문자형 LCD 를 FPGA상에서 4-비트 모드로 구동하기 위한 VHDL 코드
