유한상태머신 기반 신호등 설계 및 구현

문서 내 토픽

1. Finite State Machine (FSM)

FSM은 유한한 개수의 구분되는 상태를 가지는 시스템으로, 한 번에 하나의 상태만 가질 수 있으며 상태 전환은 순식간에 이루어진다. 현재 상태와 입력에 따라 다음 상태가 결정되는 구조이며, 상태 간의 전환을 전이(transition)라고 부른다. State diagram을 통해 시각적으로 표현되며, 상태를 나타내는 원과 상태 전환 경로를 보여주는 선으로 구성된다.
2. Mealy Machine과 Moore Machine

Mealy Machine은 입력과 현재 상태에 의해 출력이 결정되어 입력이 바뀔 때마다 출력이 즉각적으로 변경되며, 일반적으로 더 적은 수의 상태로 설계 가능하다. Moore Machine은 출력이 현재 상태에만 의존하므로 입력이 변경되어도 상태가 바뀌기 전까지 출력이 변하지 않으며, 구조가 단순하지만 일반적으로 더 많은 상태가 필요하다.
3. Verilog HDL을 이용한 FSM 구현

Verilog HDL에서 FSM을 구현할 때 클럭 신호에 따라 모듈이 동작하도록 하며, always문과 case문을 통해 상태 전이를 정의한다. 매개변수를 선언하여 각 상태를 구분하고, 클럭 주기를 쉽게 변경할 수 있도록 unit_clk 매개변수를 추가한다. Waveform simulation과 FPGA implementation에서 서로 다른 클럭 주기를 사용할 수 있다.
4. State Transition Table과 State Diagram

State transition table은 FSM의 동작을 요약하는 표로 현재 상태, 현재 입력, 다음 상태, 출력 정보를 포함한다. 각 행은 서로 다른 상태를, 각 열은 입력 기호를 나타내며, 1차원 또는 2차원으로 표현 가능하다. State diagram은 상태를 원으로, 상태 전환 경로를 선으로 표현하여 FSM을 시각적으로 설명한다.

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1. Finite State Machine (FSM)

Finite State Machines are fundamental computational models that form the backbone of digital system design. FSMs provide an elegant way to model systems with discrete states and transitions, making them invaluable for sequential logic design. Their simplicity and deterministic nature make them ideal for hardware implementation and protocol design. However, FSMs have limitations when dealing with complex systems requiring extensive memory or hierarchical state structures. Despite these constraints, FSMs remain essential in embedded systems, microcontroller programming, and digital circuit design. Their mathematical foundation ensures predictable behavior and facilitates formal verification. The ability to represent FSMs visually through state diagrams enhances their educational value and practical applicability in real-world engineering projects.
2. Mealy Machine과 Moore Machine

Mealy and Moore machines represent two distinct approaches to FSM design, each with specific advantages and trade-offs. Mealy machines, where outputs depend on both current state and inputs, offer more compact designs with fewer states and faster response times. Moore machines, with outputs dependent solely on current state, provide simpler output logic and better synchronization properties. The choice between them depends on application requirements: Mealy machines excel in systems requiring immediate input-dependent responses, while Moore machines suit applications needing stable, synchronized outputs. Understanding both models is crucial for optimal FSM design. In practice, hybrid approaches combining both paradigms often yield the best results. The theoretical equivalence between these models demonstrates the flexibility of FSM design methodology.
3. Verilog HDL을 이용한 FSM 구현

Verilog HDL provides powerful constructs for implementing FSMs efficiently in hardware design. The language's support for parameter definitions, case statements, and always blocks enables clean, readable FSM code. Verilog allows designers to implement FSMs using various styles: behavioral, structural, and mixed approaches. The ability to simulate and synthesize FSM designs directly from Verilog code significantly accelerates development cycles. However, designers must carefully manage clock domains and reset conditions to ensure reliable operation. Proper coding practices, such as using enumerated types and clear state naming conventions, enhance code maintainability. Verilog's flexibility enables optimization for specific hardware targets, whether FPGA or ASIC implementations. The language's widespread adoption in industry makes Verilog-based FSM design a practical and marketable skill.
4. State Transition Table과 State Diagram

State Transition Tables and State Diagrams are complementary tools for FSM specification and analysis. State Diagrams provide intuitive visual representations, making FSM behavior immediately comprehensible to engineers and stakeholders. They excel at showing system flow and identifying potential design issues through visual inspection. State Transition Tables, conversely, offer comprehensive tabular representations capturing all state transitions, inputs, and outputs systematically. Tables facilitate formal verification and serve as direct references for implementation. The combination of both representations provides complete documentation: diagrams for conceptual understanding and tables for detailed implementation. Modern design tools often auto-generate one representation from the other, reducing manual effort. Effective FSM design requires proficiency with both formats, as each reveals different aspects of system behavior and helps identify edge cases or missing transitions.

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