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[전기전자응용실험] Analog 통합보고서

2009-1 EE Electrical & Electronic Engineering ExperimentsChapter 1∼5.Total Result ReportElectrical and Electronic EngineeringFinal Report학 과학 년학 번분 반실험조성 명전기전자공학3학년전기전자공학3학년▷ Regulator① compare and contrast the characteristics of 6.1.1, 6.1.2, and 6.1.3.- fixed output voltage(LM7805)Design 6.1.1?The test of the regulator are above graph. It means that the experiment is succeeded and the output of above 6.5V is regulated 5V.- variable output voltageDesign 6.1.2?The test of the regulator are above graph. First graph, output of above 9.5V is regulated 8V. Second graph, output of above 11.5V is regulated 12V. Third graph, output of above 16.5V is regulated 15V.② Grasp the characteristics of regulators that were found during this experiment.- We alreadt know, most of electronic device is sensitive to input voltage. Regulator prevent device from variance of output voltage. Using Regulator, we control output voltage constantly. And we laso know, if the input voltage didn't exceed the limit vog sensor- The graph of data sheet and the our experiment result are almost same but there is some error. In experimental circumstance we can't measure the distance precisely. And our DC-DC Converter supply 5.02V. But maybe datasheet's voltage supply is 5V. So voltage supply's error caused graph's error.② Check if there is a difference in the result when the input of the oscilloscope is AC and DC. If any discrepancy exists, explain- If we choose the DC voltage, that shows the output voltage value as same as the graph first. But when we simulate at AC voltage, it likes establish capacitor in the input. Because of the Capacitor works as high pass filter, that means block low frequency. So, if there is a distance variation between sensor and object, wave changes more slightly than DC voltage.▷ RC filtersPspice Schematic- This schematic shows, if the output is taken across the capacitor, high frequencies are rejected and low frequencies are passed. Thus, the circuit behaves as a low-pass fi0.3125V. The result of output for 4 bit code dimension of LSB is 304㎷. We can calculate the error is=2.72% and the reason of error is maybe comes from dismeasuring during experiment. Because we can't control micro voltage precisely.② Draw the input/output graph of the upper 5-bits of the output and compare it with an ideal ADC. If any deviation exist, explain.level4bit codeIdeal(V)Real(V)00100000.31250.305200010.6250.616300100.93750.924400111.251.248501001.56251.352601011.8751.885701102.18752.175801112.52.501910002.81252.8011010013.1253.1251110103.43753.4251210113.753.7481311004.06254.0511411014.3754.3741511104.68754.67316111155.022ideal outputreal output- Our experiment focus on the upper 4-bits of the output, not the upper 5-bits of the output. And draw I/O graph using MATLAB. There is significant difference between real output and ideal output. When XX100000 goes to XX110000, there is long term steps, and this phenomenon comes from low 3bits. During low 3 bits rise, we just measure nd frequency of the waveform according to the input voltageTimer schematicfrequency, duty 공식SimulationExperimentVamp=5V(f=300, R=3000, R=500)Vamp=5V(f=300, R=3000, R=500)Vamp=7V(f=300, R=3000, R=500)Vamp=7V(f=300, R=3000, R=500)- In this experiment, we know that amplitude of input is varied. As amplitude varying, trigger frequency also varying. Above figure show variety modulated signal having variety signal width. As amplitude input is increased, the width also increased.② Analyze the change in the amplitude and frequency of the waveform according to the value of R and C.Simulationf=300, R=3k, R=500, c=0.1uf=300, R=3k, R=500, c=1uf=300, R=3k, R=500, c=10uf=300, R=300k, R=1k, c=0.01u- Because of the limited time, we didn't do changing experiment(R and C). So I'll just show PSPICE simulation result. We already know that. Above picture follows that when capacitor bigger, waveform's period become longer. Below picture follows that when resister and capacitor bigger, waveform's period becoter. We use regulator to regulate output voltage constantly. And use DC-DC converter to make the 5V from com toand -5V from com to. And we connect range-finding sensor.Second class, we experiment RrC filters and Tow-Thomas Biquid filters on bread board. But we only use RC filters in our experiment. This High Pass Filter removes DC components. When we connected sensor with HPF, we pass the hand above the sensor. Then waveform is pulsed, but when hand is still above the sensor, waveform goes back in flat waveform.Third class, we make Analog Digital Converter(ADC0804). The input is filter's output, and the output is digital code go into microprocessor. And we only use output 4 bit code. And we can check whether experiment is success or failure by examine LED's state.Fourth class, we make Digital Analog Converter. Input is microprocessor's 8 bit and output is analog voltage. But we didn't do our entire experiment in this day. Especially in our class, we did bread board experiment but we dier.

공학/기술| 2009.10.19| 12페이지| 1,000원| 조회(330)

실험, 연세대, 응용실험, 전기전자응용실험

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[전기전자응용실험] Timer and Audio Amp 예비보고서

2009-1 EE Electrical & Electronic Engineering ExperimentsChapter 5.Timer and Audio AmpElectrical and Electronic EngineeringPreliminary Report학 과학 년학 번분 반실험조성 명전기전자공학3학년전기전자공학3학년▷ how the experiment would be performedThe purpose of this experiment is to understand usage of timer and audio amp. First we commect regulator's output to timer(LM555) and buffer. And its out goes to the speaker. So, it's important to examine datasheets and materials about this experiment before we do this experiment.Timer's input is a DAC's output. And its output is variable frequency oscillation. And we design audio amp buffer. Its input is a timer's output and its output goes to the input of speaker. And finally, connect the speaker to the timer and the audio amplifier and check if the output aound changes according to the input of the timer.▷ answer to the question* 4.1 Timer① Refer to the datasheet of LM555 and design a circuit that satisfies the circuit specification listed in 6.1 using PSPICE program. Use 555D component.- we know that,and we know a tendency. In the self running system the modulation charge time is calculated as 0.693. So there is a gap between experiment and theory. But there exists a certain point that we must set up the frequency range in audibility range. So it is inin the abstract. In the schematic duty it cannot be 0.5 because if, it makes circuit break(floating circuit). So typically in datasheet the duty is 0.3. And we will use a register 390㏀ and 300㏀ and 0.1㎋ capacitors and R=1㏀.LM555f-c graphLM555 schematic(c=0.1㎋)f-c graph(c=0.1㎋)LM555 schematic(c=0.01㎋)f-c graph(c=0.01㎋)② Refer to the datasheet of LM555 and research various functions of the device other than pulse width modulation and pulse position modulation.LM555waveforms- This is another application of LM555. It is called frequency divider. I found it in internet database. The monostable circuit can be used as a frequency divider by adjusting the length of the timing cycle. Upper graph shows the waveforms generated in a divide by three circuit.* 4.2 Audio Amp① Refer to the datasheet of LM386 and design a circuit that satisfies the design specifications listed on 6.2. Include circuit topology and component values. Other structures of audio amps are also acceptable if the design specifications are satisfied.LM386 schematic(gain=20)② Select an IC other than LM386 that are designed for audio amps and research the characteristics. Refer to the website www.alldatasheet.com.LM4730 schematic- The LM4730 is a stereo audio amplifier delivering typically 14W per channel of continuous average output power into a 4Ω or 8Ω load with less than 10% THD+N from 20㎐∼20000㎐. Each amplifier has an independent smooth transition fade in/out mute and a power conserving standby mode which can be controlled by external logic. The LM4730 has short circuit protection and a thermal shut down feature that is activated when the die temperature exceeds 150°C. The LM4730 also has a under voltage lock out feature for click and pop free power off and on. The LM4730 has a wide operating supply range from +/-10V - +/-25V allowing for lower cost unregulated power supplies to be used. It has n Minimal amount of external components necessary and n Quiet fade-in/out mute mode and n Low current Standby-mode.

공학/기술| 2009.07.29| 5페이지| 1,000원| 조회(266)

연세대, 응용실험, 전기전자응용실험

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[전기전자응용실험] Timer and Audio Amp 결과보고서

2009-1 EE Electrical & Electronic Engineering ExperimentsChapter 5.Timer and Audio AmpElectrical and Electronic EngineeringFinal Report학 과학 년학 번분 반실험조성 명전기전자공학3학년전기전자공학3학년▷ answer to the questionTimer와 회로를 연결LM555의 input 신호LM555의 output 파형완성된 회로* 7.1 Timer① Analyze the change in the amplitude and frequency of the waveform according to the input voltageTimer schematicfrequency, duty 공식SimulationExperimentVamp=5V(f=300, R=3000, R=500)Vamp=5V(f=300, R=3000, R=500)Vamp=7V(f=300, R=3000, R=500)Vamp=7V(f=300, R=3000, R=500)- In this experiment, we know that amplitude of input is varied. As amplitude varying, trigger frequency also varying. Above figure show variety modulated signal having variety signal width. As amplitude input is increased, the width also increased.② Analyze the change in the amplitude and frequency of the waveform according to the value of R and C.Simulationf=300, R=3k, R=500, c=0.1uf=300, R=3k, R=500, c=1uf=300, R=3k, R=500, c=10uf=300, R=300k, R=1k, c=0.01u- Because of the limited time, we didn't do changing experiment(R and C). So I'll just show PSPICE simulation result. We already know that. Above picture follows that when capacitor bigger, waveform's period become longer. Below picture follows that when resister and capacitor bigger, waveform's period become longer than input signal period. In conclusion, the larger capacitor makes higher frequency and the larger register makes higher frequency, too.* 7.3 Speaker① What is the reason the speaker output sound changes according to the timer's output?- Speaker's sound volume is related with input signal's amplitude. and speaker's tone related with input frequency. Timer's ability is generating frequency relative with input's amplitude. So when timer's output become different, not their sound volume change, but speaker's tone is change.

공학/기술| 2009.07.29| 5페이지| 1,000원| 조회(201)

연세대, 응용실험, 전기전자응용실험

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[전기전자기초실험] FSM 설계 실험 예비보고서

학 과학 년학 번분 반실험조성 명전기전자공학2학년전기전자공학2학년① 상태천이표와 상태도 verilog HDL을 이용하여 구현module fsm_state (clk, in, out, state);input clk, in;output out;output[3:0]state;reg out;reg [3:0]state;parameter [2:0] state0=0, state1=1, state2=2, state3=3, state4=4;always @ (posedge clk) beginif (in) begincase(state)state0 :beginstate=state1;out=0;endstate1 :beginstate=state2;out=1;endstate2 :beginstate=state3;out=0;endstate3 :beginstate=state4;out=1;endstate4 :beginstate=state0;out=0;endendcaseendelse begincase(state)state0 :beginstate=state0;out=0;endstate1 :beginstate=state0;out=0;endstate2 :beginstate=state0;out=0;endstate3 :beginstate=state3;out=0;endstate4 :beginstate=state0;out=0;endendcaseendendendmodule② 초콜렛 자판기 제어기 verilog HDL을 이용하여 구현module chocolate (clk, in, out, state);input clk;input[1:0]in;output out;output[1:0]state;reg out;reg [1:0]state;parameter [1:0] S0=0, S50=1, S100=2, S150=3;always @ (posedge clk) beginif (state==S0) begincase(in)2'b00 : state=S0;2'b01 : state=S50;2'b10 : state=S100;endcaseout=0;endelse if (state==S50) begincase(in)2'b00 : state=S50;2'b01 : state=S100;2'b10 : state=S150;endcaseendelse if (state==S100) begincase(in)2'b00 : state=S100;2'b01 : state=S150;2'b10 : state=S150;endcaseendelse beginstate=S0;out=1;endendendmodule③ 차량 속도 제어기 verilog HDL을 이용하여 구현module velocity_control (key, clk, acc, br, state);input key, clk, acc, br;output[1:0]state;reg [1:0]state;parameter [1:0] Stop=0, Slow=1, Medium=2, Fast=3;always @ (posedge clk) beginif (key==1) beginif (state==Stop) beginif (acc)state=Slow;elsestate=Stop;endelse if (state==Slow) beginif (br)state=Stop;else if (acc)state=Medium;elsestate=Slow;endelse if (state==Medium) beginif (br)state=Slow;else if (acc)state=Fast;elsestate=Medium;endelse if (state==Fast) beginif (br)state=Medium;elsestate=Fast;endendelse if (key==0)state=Stop;endendmodule④ 교통신호 제어기 상태도 작성, verilog HDL을 이용하여 구현StateDescriptionS0Highway GREENFarm REDS1Highway YELLOWFarm REDS2Highway REDFarm REDS3Highway REDFarm GREENS4Highway REDFarm YELLOWmodule traffic_control(clk, C, HL);input clk;input C;output [5:0] HL;reg [5:0] HL;always@(posedge clk) begincase(HL)6'b100001: begin if (C == 1'b1) HL = 6'b010001;else if(C == 1'b0) HL = 6'b100001;end6'b010001: begin if (C == 1'b1) HL = 6'b001001;else if (C == 1'b0) HL = 6'b010001;end6'b001001: begin if (C == 1'b1) HL = 6'b001100;else if (C == 1'b0) HL = 6'b001001;end6'b001100: begin if (C == 1'b1) HL = 6'b001010;else if (C == 1'b0) HL = 6'b001010;end6'b001010: begin if (C == 1'b1) HL = 6'b100001;else if (C == 1'b0) HL = 6'b100001;enddefault : HL = 6'b100001;endcaseendendmodule

공학/기술| 2009.07.29| 5페이지| 1,000원| 조회(375)

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[전기전자응용실험] Analog-to-Digital Converters 예비보고서

2009-1 EE Electrical & Electronic Engineering ExperimentsChapter 3.Analog-to-Digital ConvertersElectrical and Electronic EngineeringPreliminary Report학 과학 년학 번분 반실험조성 명전기전자공학3학년전기전자공학3학년▷ how the experiment would be performedThe purpose of this experiment is to understand usage of ADC and make a circuit that generates output within the desired range. So, it's important to examine datasheets and materials about this experiment before we do this experiment.In experiment progress, We'll design ADC circuits and connecting that circuit to microprocessors. First, we use ADC0804(using ADC and Lamp, swtch and some circuit elements). Input is a output of filter which was built last time. After that, the output is 8 bits AD conversion.The next is a connecting process. The code which takes an 8 bits input and display it into 2 sets of 7 segment values from 0 to F. And we must check that the correct output values show up on 7 segment.▷ answer to the question① Refer to the datasheet of ADC0804 and study what each pin represents.ADC0804?(Pin 1)/CS(Chip Select) : It means to use the device choose the pin[Low Active Pin](Pin 2)/RD(Read) : Order generating data to a data line to read a data from the device.(Pin 3)/WR(WRITE) : Ordering to start ADC about analog signal(Pin 4)/CLK IN(Clock In) : generate internal clock, this pin will connect some resistor and capacitor.(Pin 5)/INTR(Interrupt) : This pin will put out signal that end of converting analog to digital.(Pin 6)/VIN +(Voltage In +) : Connecting input voltage that will convert.(Pin 7)/VIN -(Voltage In -) : Connecting input voltage's ground.(Pin 8)/A GND(Analog Ground) : Ground of analog voltage.(Pin 9)/VREF / 2(Reference Voltage / 2) : This pin will conclude input range. Generally, this pin receive reference voltage ÷ 2. If this pin open, input range is 0∼VCC.(Pin 10)/D GND(Digital Ground) : Ground of digital voltage.(Pin 11∼18)/DB7∼DB0(Digital Bit) : Converted digital signals.(8 bit)(Pin 19)/CLK R(Clock Out) : To generate internal clock, this pin will connect some resistor and capacitor.(Pin 20)/VCC or VREF : Connecting source voltage.② Refer to the datasheet of ADC0804 and design a circuit that satisfies the design specifications listed on 6.1. Include the circuit topology and component values.design a ADC0804 circuit- By ADC0804 datasheet, we make a schematic circuit. Last experiment we made a filter with some capacitor and register. So we can use a input that sensor's Output which is filtered by RC filter. As we measure before that it was 3.2V in 7cm but for accuracy, we do that experiment againand use the maximum output.which comes from regulator. And CLK R and CLK IN are connected as above. And use 10㏀ register and 150㎊ capacitor. In ths experiment there is a caution point in digital ground and analog ground. analog ground using high impedence. so if we regard A-gnd and D-gnd same, then there must be error.③ Assume that 6-bit SAR ADC with the input range of 0∼5V and the input voltage of 0.7V or 3.4V. Draw the state transition diagram of the specified SAR.SAR state diagram- There must exist two input 0.7V or 3.4V and input signal range is 0∼5V. N-bit converter can divide state onlybits. because of 6 bits aren'tbits that makes like above diagram and the upper two input signal is waste bits. And we define the two inputs 0.7V and 3.4V so it doesn't matter the upper bit.

공학/기술| 2009.07.29| 4페이지| 1,000원| 조회(416)

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