MOT2_ROT library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity mot2_rot is port( CLK_4M, RSTB, MTP_SW1, MTP_SW2, MTP_SW3, MTP_SW4 : in std_logic MTR_A, MTR_B, MTR_nA, MTR_nB, MTL_A, MTL_B, MTL_nA, MTL_nB : out std_logic ); end mot2_rot; architecture behave of mot2_rot is signal key_in_l : std_logic_vector(1 downto 0); signal key_in_r : std_logic_vector(1 downto 0); signal speed_l : integer range 0 to 25000; signal speed_r : integer range 0 to 25000; signal motor_lcnt : integer range 0 to 25000; signal phase_lclk : std_logic; signal motor_rcnt : integer range 0 to 25000; signal phase_rclk : std_logic; signal phase_lcnt : std_logic_vector(1 downto 0); signal phase_lout : std_logic_vector(3 downto 0); signal phase_rcnt : std_logic_vector(1 downto 0); signal phase_rout : std_logic_vector(3 downto 0); begin key_in_l <= (MTP_SW1 & MTP_SW2); key_in_r <= (MTP_SW3 & MTP_SW4);
CNT_4 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity cnt_4 is port( clk : in std_logic; rst : in std_logic; cnt_out : buffer std_logic_vector(3 downto 0); clk_out : buffer std_logic ); end cnt_4; architecture behave of cnt_4 is signal temp : std_logic_vector(2 downto 0):="000"; begin process(clk, rst) begin if rst=`1` then if clk`event and clk=`1` then cnt_out<=cnt_out + 1; end if; else cnt_out<="0000"; end if; end process; process(clk, rst) begin if rst=`0` then temp<="000"; clk_out<=`0`; else if clk`event and clk=`1` then temp <= temp + 1; if temp="100" then temp<="000"; clk_out <= not clk_out; end if; end if; end if; end process; end behave;
1Bit Library IEEE; use IEEE.std_logic_1164.all; entity bit_1 is port( A, B : in std_logic; EQ : out std_logic ); end bit_1; architecture behave_bit_1 of bit_1 is begin process(A, B) begin if A = B then EQ <= `1`; else EQ <= `0`; end if; end process; end behave_bit_1; ? 1Bit Test Bench Library IEEE; use IEEE.std_logic_1164.all; entity tb_bit_1 is end tb_bit_1; architecture tb_behave of tb_bit_1 is signal A, B, EQ : std_logic; component bit_1 port( A, B : in std_logic; EQ : out std_logic ); end component;
RAM Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ram is port( CE, RD, WR : in std_logic; ADDR, IN_DATA : in std_logic_vector(3 downto 0); OUT_DATA : out std_logic_vector(3 downto 0) :=(others=>`0`) ); end ram; architecture behave of ram is type RAM_WORD is array (0 to 15) of std_logic_vector(3 downto 0); signal RAM_DATA : RAM_WORD := ("0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000"); begin process(CE, RD, WR, ADDR, IN_DATA) begin if (CE=`0`) then if (WR=`0`) then RAM_DATA(conv_integer(ADDR))<=IN_DATA; elsif (WR=`1` and RD=`0`) then OUT_DATA<=RAM_DATA(conv_integer(ADDR)); end if; end if; end process; end behave;
CNT0 -- 비동기 카운터의 4비트 카운터에서 clk_out값만 빼고 설계 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity cnt0 is port( clk, rst : in std_logic; cnt_out : buffer std_logic_vector(3 downto 0) ); end cnt0; architecture behave of cnt0 is begin process(clk, rst) begin if rst = `1` then if clk`event and clk =`1` then cnt_out <= cnt_out+`1`; end if; else cnt_out <= "0000"; end if; end process; end behave; CNT1 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity cnt1 is port( clk, rst : in std_logic; cnt_out : buffer std_logic_vector(3 downto 0) ); end cnt1; architecture behave of cnt1 is signal add : std_logic_vector(2 downto 0):=(others => `0`);-- clk상승을 세기위한 임시 신호 add signal divi : std_logic:=`0`;-- add에 따라 분주를 나누기 위한 임시 신호 divi begin process(clk, rst) begin if rst = `1` then if clk`event and clk =`1` then if add = "100" then add <= (others => `0`);
