연세대 전기전자공학부 20-1학기 기초아날로그실험 7주차 예비레포트

소개

연세대 전기전자공학부 20-1학기 기초아날로그실험 7주차 예비레포트입니다.
이 보고서 성적은 만점(40/40)이며, 최종 성적은 A+를 받았습니다.

목차

Ⅰ. Part 1
1.Theory
1-1Kirchhoff’s Current Law (KCL)
1-2Kirchhoff’s Voltage Law (KVL)
1-3Diode
1-4Rectifier
2.PSPICE simulation
2-1 Experiment 1: KCL & KVL
2-2 Experiment 2: RLC series circuit
2-3 Experiment 3: RLC parallel circuit
2-4 Experiment 4: Full Wave Bridge Rectifier

Ⅱ. Part 2
1.Theory
1-11st order & 2nd order active filter
1-2Sallen-Key Filter
1-3Tow-Thomas Biquad Filter
2.PSPICE simulation
2-1 Experiment 1: 1st order & 2nd order LPF
2-2 Experiment 2: 1st order & 2nd order HPF
2-3 Experiment 3: Tow-Thomas biquad filter
3.Reference

본문내용

In this part, the goal is to understand the passive component (R, L, C) and diode, construct the circuit composed of R, L, C, and measure the values using PSPICE simulation.

Theory
Kirchhoff’s Current Law (KCL)
Kirchhoff's current law (KCL) states that the algebraic sum of the currents flowing into certain node is zero. That is, the amount of incoming current is same as the amount of outgoing current.
The expression shown in the [Figure 1-1] is expressed in a formula as follows.
I_1+I_2+I_3+I_4+I_5=0
In general, it can be expressed as ∑_(j=1)^N▒〖i_j (t)〗=0.

[Figure 1-1] KCL

Consider the circuit as shown in [Figure 1-2] below.

[Figure 1-2] Example circuit
Apply KCL at node 2, ∑▒I_entering =∑▒I_leaving .
I_R1+I_R3=I_R2 , (V_0-V_2)/1.0k+(V_1-V_2)/2.2k=(V_2-V_3)/3.7k
Apply KCL at node 3,
(V_2-V_3)/3.7k=(V_3-V_0)/5.4k
At node 1, V1 = 3V due to source, At node 0, V0 = 0V due to ground.

Kirchhoff’s Voltage Law (KVL)
Kirchhoff's voltage law (KVL) states that the algebraic sum of the electrical potential difference in any closed loop is zero.
That is, the electromotive force is same as the amount of voltage drop in closed loop.
The expression shown in the [Figure 1-3] is expressed in a formula as follows.

참고자료

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