디지털시스템) Verilog를 이용한 Single cycle 구현

소개

Verilog를 이용한 Single cycle구현

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Verilog

본문내용

module top (clk,res,x);
input clk,res,x;
wire [31:0]instruction,Read_data1,Read_data2,ALU_result,ReadData;
wire [31:0]Branch_result,Jump_address,add_out,pc_out,ALUSrc_out;
wire [31:0]shift_out1,MemtoReg_out,shift_out2,sign_outALUSrc_out,sign_out,Jump_out,Branch_out;
wire RegWrite,RegDst,ALUSrc,zero,MemWrite,MemRead,MemtoReg,Branch,Jump;
wire Carry;
wire [4:0]RegDst_out;
wire [3:0]ALU_control_lines;
wire [1:0]ALUOp;

PC p0(clk,x,res,Jump_out,pc_out);
Add a0(pc_out,32'h00000004,add_out);
Instruction_memory im0(pc_out, instruction);
Register r1(clk,instruction[25:21],instruction[20:16],RegDst_out,MemtoReg_out,RegWrite,Read_data1,Read_data2);
Mux2 m1(instruction[20:16],instruction[15:11],RegDst,RegDst_out);
ALU32 alu1(Read_data1,ALUSrc_out,ALU_control_lines,ALU_result,zero);
Mux32 m2(Read_data2,sign_out,ALUSrc,ALUSrc_out);
Sign_extend s1(instruction[15:0],sign_out);
data_memory d1(clk,ALU_result,Read_data2,ReadData,MemWrite,MemRead);
Mux32 m3(ALU_result,ReadData,MemtoReg,MemtoReg_out);
Control_Unit c1(instruction[31:26],zero,RegDst,ALUSrc,MemtoReg,RegWrite
,MemRead,MemWrite,Branch,ALUOp,Jump);
ALU_Control c2(ALUOp,instruction[5:0],ALU_control_lines);
Shift_left sl1(sign_out,shift_out1);
Add a1(add_out,shift_out1,Branch_result);
Mux32 m4(add_out,Branch_result,Branch,Branch_out);
Mux32 m5(Branch_out,Jump_address,Jump,Jump_out);
Shift_left sl2(instruction,shift_out2);

assign Jump_address[31:28] = add_out[31:28];
assign Jump_address[27:0] = shift_out2[27:0];

endmodule

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