multi-cycle MIPS implementation

소개글

32-bit multi cycle MIPS microprocessor 를 Quartus를 사용하여 design 했습니다.

목차

1. Objectives
2. Design Requirements
3. Simulation Result
4. Simulation Analysis
5. Discussion

본문내용

1. Objectives
- To learn the basic structure and operation of the Multi-cycle MIPS processor

2. Design Requirements
32-Bit Multi-Cycle MIPS Microprocessor Design
The MIPS processor to be implemented for this lab assignment is identical to the multi-cycle MIPS processor in Chapter 5. The schematic for the multi-cycle implementation is also included in the following diagram. The requirements for the project are to implement and complete the datapath and control logic for multicycle
implementation; major tasks include completion of the design and simulation of the ten instructions: add, sub, and, or, slt, sw, lw, beq, addi, jump. The operations of each instruction follow the descriptions given in the textbook. The design is implemented hierarchically with several block structures. The operation and internal
structure of each block are identical to the descriptions in the textbook.

3. Simulation Result
(1) Schematic diagram

(3) Source Code
① Control_multi.v
module control_multi(OPcode, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcA, ALUSrcB, RegWrite, RegDst, state, clk);

input [5:0] OPcode;
input clk;
output [1:0] PCSource, ALUOp, ALUSrcB;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;

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