결과보고서-Exp 8. Co-Simulation & Co-Emulation Using FPGA.hwp

소개

결과보고서-Exp 8. Co-Simulation & Co-Emulation Using FPGA.hwp

목차

1. Purpose
2. Problem Statement
3. Experimental Procedure & Result
4. Source code & Comment
5. The reason why the result of Co-Emulation is different from that of Simulation.
6. Conclusion & Discussion
7. Reference

본문내용

1. Purpose
Before the exp.9 and exp.10 in which you should design a complex digital circuit in verilog HDL, we are going to deal with a digital circuit design-flow using a simple adder. You can learn how to do the followings in this experiment.

- Digital circuit design in verilog HDL
- Software Simulation with a test-bench
- H/W Synthesis
- Co-Simulation/Emulation with a FPGA board

2. Problem Statement
Design a simple 4-bit Ripple Carry Adder in verilog HDL and simulate it with a test-bench. Then Do Co-Simulation/Emulation using the FPGA board – “iNCITE”.

3. Experimental Procedure & Result
1) Design a test-bench
A test-bench is a virtual environment to verify the correctness of the design. Design a test-bench for the given 4-bit Adder. The test-bench should include the generator of clock & inputs of the adder.

우리는 다음과 같이 test-bench를 작성하였으며 4. source code & comment에서 좀 더 세부적으로 comment를 작성하도록 하겠다.

`timescale 1ns / 1ps
module test_v;

`ifdef _iNCITE_
parameter iPROVE_EIF_FILE="../inspire/par/fpga0.eif";
`endif

// Inputs
reg clk;
reg [3:0] A;
reg [3:0] B;
reg CI;

// Outputs
wire [3:0] Z;

참고자료

· - Ando Ki, “FPGA-Based Simulation for Rapid Prototyping”, Xcell Journal, Third Quarter 2007.
· - Dynalith Systems, “iNCITE and iNSPIRE-Lite Quick Tutorial”, Mar. 2007.
· - Dynalith Systems, “iNSPIRE-Lite Installation Manual”, Dec. 2006.
· - 홍를과학출판사, “ISE를 이용한 Verilog HDL 및 FPGA 실습.”, Aug. 2006