HEVC VLSI 디블로킹 필터를 위한 메모리 할당 기반의 설계 (Memory Allocation-based VLSI Design for HEVC Deblocking Filter)

서지정보

· 발행기관 : 대한전기학회
· 수록지 정보 : 전기학회논문지 / 69권 / 11호 / 1755 ~ 1760페이지
· 저자명 : 김현준, 배종우

초록

In this paper, we propose a high-performance VLSI architecture and memory allocation algorithm for HEVC Deblocking Filter. For high-performance VLSI design, a parallel architecture is employed. Our architecture employs 8 parallel filters and 4-stage pipeline to meet the high-performance video requirements. In the implementation of highly parallel VLSI architecture, high bandwidth and low latency memory access is very important. A novel memory allocation algorithm is proposed to reduce the on-chip SRAM access conflicts between the parallel filters. By storing 4x4 pixel blocks used for the computation of parallel filters into different SRAM blocks, the data for horizontal and vertical filtering can be accessed without conflicts. Therefore, the maximum on-chip SRAM throughput is maintained during the filtering computation. The proposed architecture can process video of 16K (15360x8640) at 60fps in real time. The VLSI implementation of the proposed architecture operates at 140MHz and the gate count is 244K in TSMC 65nm process. Compared with the previous works, the proposed work shows the performance improvement of 90%.

영어초록

In this paper, we propose a high-performance VLSI architecture and memory allocation algorithm for HEVC Deblocking Filter. For high-performance VLSI design, a parallel architecture is employed. Our architecture employs 8 parallel filters and 4-stage pipeline to meet the high-performance video requirements. In the implementation of highly parallel VLSI architecture, high bandwidth and low latency memory access is very important. A novel memory allocation algorithm is proposed to reduce the on-chip SRAM access conflicts between the parallel filters. By storing 4x4 pixel blocks used for the computation of parallel filters into different SRAM blocks, the data for horizontal and vertical filtering can be accessed without conflicts. Therefore, the maximum on-chip SRAM throughput is maintained during the filtering computation. The proposed architecture can process video of 16K (15360x8640) at 60fps in real time. The VLSI implementation of the proposed architecture operates at 140MHz and the gate count is 244K in TSMC 65nm process. Compared with the previous works, the proposed work shows the performance improvement of 90%.

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