다구찌 기법을 활용한 반도체 연마 공정의 최적 설계수준 결정 (Determination of Optimal Design Level for the Semiconductor Polishing Process by Taguchi Method)

서지정보

· 발행기관 : 한국품질경영학회
· 수록지 정보 : 품질경영학회지 / 45권 / 2호 / 293 ~ 306페이지
· 저자명 : 심현수, 김용수

초록

Purpose: In this study, an optimal design level of influencing factors on semiconductor polishing process was determined to minimize flexion of both sides on wafers.
Methods: First, significant interactions are determined by the stepwise regression method. ANOVA analysis on SN ratio and mean of dependent variable are performed to draw mean adjustment factors. In addition, the optimal levels of mean adjustment factors are decided by comparing means of each level of mean adjustment factors.
Results: As a result of ANOVA, a mean adjustment factor was determined as a width of formed flexion on the plate. The mean of the difference has the nearest to 0 in the case when the width of formed flexion has level 2 (4mm).
Conclusion: Optimal design levels of semiconductor polishing process are determined as follows; (i) load applied to the wafer carrier has a level 1 (3psi), (ii) load applied to the wafer has a level 1(3psi), (iii) the amount of slurry supplied during polishing has a level 3 (300 co/min), (iv) the width of formed flexion on the plate has level 2 (4mm).

영어초록

Purpose: In this study, an optimal design level of influencing factors on semiconductor polishing process was determined to minimize flexion of both sides on wafers.
Methods: First, significant interactions are determined by the stepwise regression method. ANOVA analysis on SN ratio and mean of dependent variable are performed to draw mean adjustment factors. In addition, the optimal levels of mean adjustment factors are decided by comparing means of each level of mean adjustment factors.
Results: As a result of ANOVA, a mean adjustment factor was determined as a width of formed flexion on the plate. The mean of the difference has the nearest to 0 in the case when the width of formed flexion has level 2 (4mm).
Conclusion: Optimal design levels of semiconductor polishing process are determined as follows; (i) load applied to the wafer carrier has a level 1 (3psi), (ii) load applied to the wafer has a level 1(3psi), (iii) the amount of slurry supplied during polishing has a level 3 (300 co/min), (iv) the width of formed flexion on the plate has level 2 (4mm).

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