Semiconductor Device and Design - 9-10__

목차

1. Layout of the 1bit adder and subtracter
2. Function of the 1bit adder and subtracter
3. Function of the parallel adder circuit.
4. Layout of the parallel adder circuit.

본문내용

1. Firstly the full adder FA1 adds A1 and B1 along with the carry C1 to generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to the next adder in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate the sum S2(the second bit of the output sum) and the carry C3 which is again further connected to the next adder in chain and so on.
3. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and Bn to generate the last bit of the output along last carry bit Cout.

참고 자료

Basic Electronics for Scientists and Engineers : Dennis L. Eggleston
http://www.ianhung.com/wp-content/uploads/2009/12/sequential-adder-report.pdf
https://technobyte.org/parallel-adder-subtractor/
https://techweb.rohm.co.kr/knowledge/si/s-si/03-s-si/4873