연세대학교 기초디지털실험 4주차 예비레포트 (sequential logic)

목차

Ⅰ. Reseach on Theory
1. Clock signal
2. R-S Latch
3. D F/F
4. Shift register
5. BCD Counter

Ⅱ. Reference

본문내용

1. Clock signal
Clock signal is a signal oscillating between 1, high and 0, low like pic 1. It is made by clock generator and can be represented as the square wave. It is quite important for logic circuit, because digital circuit usually use the clock signal for synchronization.
They can be active simultaneously, and for storage element, the state can be changed by receiving new value. The sequential circuits usually use the regular pulse with constant frequency, fast varying edges, and correct logic levels. There are high level(1), low level(0), falling edge and rising edge. Falling edge is the edge that state changes from high to low and Rising edge is the reverse. The clock period is represented as sum of high duration and low duration, which is same with the time from rising edge to next rising edge.

참고자료

· Yonsei univ. Electrical Electronic Engineering - Week 4 lecture
· Charles H. Roth, Jr.& Larry L Kinney. (2013). Fundamentals of Logic Design.
· Cengage Learning.