성균관대학교 디지털집적회로설계 cad과제 2

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"성균관대학교 디지털집적회로설계 cad과제 2"에 대한 내용입니다.

목차

1. Design an inverter, a 2-input NAND gate, a 2-input NOR gate, and a 2-input XOR gates, and create schematics and symbols of these logic gates. These logic gates will be used as standard cells for designing other more complex logic gates (such as 2:1 MUX in following section) Verify the functionality of these logic gates you have designed with transient simulations, which include all possible input combinations. Attach screenshots of schematic, symbols and simulation result (waveform) to report.
2. Design a 2:1 MUX using three 2-input NAND gates and one inverter, and create schematic and symbol for it. Verify the functionality of the 2:1 MUX you have designed with transient simulation, which includes all possible input combinations (include 8 possible input combinations). Attach screenshots of schematic, symbols and simulation result (waveform) to report.
3. Create layouts for an inverter, a 2-input NAND gate, 2-input NOR gate, 2-input XOR gate. Attach a screenshots of your layouts.
4. Using standard cell layouts created in #3, create a layout for the 2:1 MUX. Attach a screenshot of your layout.
5. Run DRC/LVS of the 2:1 MUX layout using Assura. Capture your DRC/LVS logs like below and attach it in report. (You should attach 3 screenshots.)

본문내용

2) 2-input NOR
A B Vout
0 0 1
0 1 0
1 0 0
1 1 0 이 정상적으로 작동함을 확인할 수 있다.
PMOS가 직렬로 연결되어서 Wp를 2배 키워준다.
Wp= 720n, Wn = 240n

3)2-input NAND
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0 이 정상적으로 작동함을 확인할 수 있다.
NMOS 2개가 직렬 연결되어서 Wn을 2배 키워준다.
Wp = 360n , Wn = 480n

4)2-input XOR
A B Vout
1 0 1
1 1 0
0 1 1
0 0 0
으로 XOR 연산이 잘 작동함을 확인할 수 있다.
NMOS와 PMOS가 모두 직렬연결 되어있어서 W를 2배씩 키워주었다.
Wp = 720n, Wn = 480n
Input의 입력 신호를 반전시키는 inverter의 pmos와 nmos의 w는 inverter이기 때문에 변경하지 않았다.

참고자료

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