Instruction Set Architecture (ISA) 비교 레포트 (MIPS, Alpha, x86, POWERpc, SPARC)
- 최초 등록일
- 2011.12.10
- 최종 저작일
- 2011.12
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MS 워드
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소개글
운영시스템 수업 영어 레포트 자료입니다.
MIPS, Alpha, x86, POWERpc, SPARC 명령어 집합 비교입니다.
칭찬 받았습니다
도움 되시길 바랍니다!
목차
1. Overview of characters
2. Design
(1) CISC
(2) RISC
3. ISA comparison
(1) MIPS
(2) Alpha
(3) x86
(4) POWERpc
(5) SPARC
본문내용
1. Design
CISC is the initial of Complex Instruction Set Computer. x86 is designed in CISC.
Most of computer made in 2008 is designed in x86.
CISC stores all instruction set. It has a lot of addressing modes and instruction lengths are variable. The number of instructions is around 100~250.
In CPU memory, there are a lot of instructions that manufactures operands.
RISC is the initial of Reduced Instruction set Computer
POWERpc, MIPS, DEC Alpha and SPARC architectures are designed in RISC.
RISC has only mostly-used-instructions. Complex operation is made by combining of simple instructions. So instruction length is fixed. And RISC is faster than CISC.
The operands are manufactured by registers in CPU.
The number of instruction is around 30~100.
2. MIPS
MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC instruction set architecture developed by MIPS Technologies. The early MIPS architectures were 32-bit, and later versions were 64-bit. What I will explain below is the early MIPS(32-bits)
MIPS operates Arithmetic instruction, Logical, Conditional branch, Unconditional jump and Data Transfer.
Here are the instruction formats of MIPS. As below, MIPS has 3 types of instructions formats which are R, I, J instructions.
It has a fixed instruction length of 32 bits
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