finite state machine design(예비)

소개

finite state machine design(예비)

목차

1. Objective

2. Theory
(1) Finite State Machine
(2) State transition table and state map

3. Reference

본문내용

2. Theory
(1) Finite State Machine
FSM is a circuit that has finite states and changes states sequentially. FSM has two basic models, Mealy model and Moore model. Mealy model is a state machine whose output relies on the current state and the input. But Moore model only relies on the current state. In the two models, the states are expressed by binary signals called the state coefficients. States coefficients are saved in the flip-flops, called state registers, which is activated by outer clock input. State register to save the current state, Combinational circuit to transit the state sequentially, and another combinational circuit to achieve the appropriate output values. The input and output of current state register are inputted into the output logic circuit to decide the output and are maintained for a clock period. The next state combination happens when the input signal and the current state register are saved.

참고자료

· - Contemporary Logic Design ( 2th Edition ), Randy H.Katz
· - Wikipedia dictionary
· - Naver 백과사전
· - Fundamental of Logic Design ( 5th Edition ), Charles H. Roth jr