웨어러블 디바이스용 집적회로설계_논문요약과제

문서 내 토픽

• 1. A 256kb Sub-threshold SRAM in 65nm CMOS

  이 논문은 기존 6T SRAM의 문제점을 해결하고자 합니다. 첫번째로는 0.7V의 Threshold Voltage 이하의 전압영역 즉, Subthreshold Voltage 영역에서 SNM 성능저하가 발생하는 것입니다. 제안된 10T SRAM은 Leakage의 영향을 막아줍니다. Leakage를 줄이면, BL 하나에 더 많은 Cell을 연결할 수 있어서 집적도가 좋아집니다.

• 2. A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme

  이 SRAM의 기본 동작을 알아보면, RWL = H일 때 READ 동작을 실시할 때 QB의 값에 따라서 RBL의 Discharge 여부가 결정됩니다. RWL = L일 때 항상 Leakage가 VDD -> M10 -> M9의 방향으로 흘러가게 되어 Leakage가 Data Dependent 하지 않게 됩니다.

• 3. A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

  6T SRAM이 가진 문제점인 Sub-Threshold 영역에서의 SNM 문제, Write inability, Unaccessed Cell의 Leakage 문제 등을 8T 구조에서 Buffered-Read, Footer 회로 등을 통해 해결했습니다. 각 Word 단위로 Foot을 공유하면 누설전류 방지의 효과를 얻을 수 있습니다.

• 4. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

  이 논문의 가장 중요한 특징은 Bit-interleaving입니다. WL은 같은 Row를 공유하고, W_WL은 같은 Column은 공유하여 Write 안정성을 높였습니다. 또한 Differential Read 방식을 사용하여 Noise tolerant하고 안정성이 좋습니다.

Easy AI와 토픽 톺아보기

• 1. A 256kb Sub-threshold SRAM in 65nm CMOS

  The paper presents the design and implementation of a 256kb sub-threshold SRAM in 65nm CMOS technology. The key focus is on improving the energy efficiency and stability of the SRAM design by operating in the sub-threshold region. The authors have addressed several challenges associated with sub-threshold SRAM design, such as read/write stability, data retention, and leakage current. The proposed design incorporates various circuit-level techniques, including a dual-rail 8T SRAM cell, a self-timed write driver, and a low-power sense amplifier, to enhance the overall performance and energy efficiency of the SRAM. The experimental results demonstrate significant improvements in terms of energy consumption, read/write stability, and data retention compared to conventional SRAM designs. This work contributes to the ongoing research in the field of ultra-low-power SRAM design, which is crucial for a wide range of applications, including IoT, wearable devices, and energy-constrained embedded systems.

• 2. A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme

  The paper presents a high-density subthreshold SRAM design with techniques to address the challenges associated with operating in the subthreshold region. The key innovations include a data-independent bitline leakage scheme and a virtual ground replica scheme. The data-independent bitline leakage scheme ensures that the bitline leakage current is independent of the stored data, improving the read stability and reducing the power consumption. The virtual ground replica scheme provides a stable reference voltage for the sense amplifier, further enhancing the read reliability. The proposed design is implemented in a 65nm CMOS process and demonstrates significant improvements in terms of energy efficiency, read/write stability, and data retention compared to conventional subthreshold SRAM designs. The high-density and energy-efficient nature of this SRAM design make it a promising candidate for a wide range of low-power applications, such as IoT devices, wearables, and energy-constrained embedded systems.

• 3. A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

  The paper presents a 65nm 8T sub-threshold SRAM design that employs a sense-amplifier redundancy scheme to improve the read reliability and energy efficiency. The key innovation is the use of multiple sense amplifiers in parallel, where only one sense amplifier is activated during a read operation. This redundancy scheme helps to overcome the challenges associated with low read margins and high bitline leakage currents in sub-threshold SRAM designs. The proposed design also incorporates other circuit-level techniques, such as a dual-rail 8T SRAM cell and a self-timed write driver, to further enhance the overall performance and energy efficiency. The experimental results demonstrate significant improvements in read stability, data retention, and energy consumption compared to conventional sub-threshold SRAM designs. This work contributes to the ongoing research in the field of ultra-low-power SRAM design, which is crucial for a wide range of energy-constrained applications, including IoT, wearable devices, and embedded systems.

• 4. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

  The paper presents the design and implementation of a 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in a 90nm CMOS process. The key innovations include the use of a 10T SRAM cell, bit-interleaving, and a differential read scheme to address the challenges associated with subthreshold SRAM design. The 10T SRAM cell provides improved read/write stability and data retention compared to the conventional 6T cell. The bit-interleaving technique helps to mitigate the impact of process variations, while the differential read scheme enhances the read reliability by reducing the bitline leakage current. The proposed design demonstrates significant improvements in terms of energy efficiency, read/write stability, and data retention compared to previous subthreshold SRAM designs. The high-density and energy-efficient nature of this SRAM design make it a promising candidate for a wide range of low-power applications, such as IoT devices, wearables, and energy-constrained embedded systems.