Tunnel-FET Based SRAM Bit Cell Design

본 내용은 " 캡스톤 발표 자료 " 의 원문 자료에서 일부 인용된 것입니다. 2023.06.24

문서 내 토픽

• 1. MOSFET and TFET

  MOSFET는 낮은 전압에서 on/off 특성이 좋지 않고 subthreshold swing이 높은 단점이 있다. 반면 TFET는 낮은 전압에서도 on 상태를 유지할 수 있고 대기 전력이 낮은 장점이 있지만 단방향 특성과 지연 시간이 길다는 단점이 있다.

• 2. TFET Modeling

  TFET는 커패시터, 다이오드, 저항으로 구성된 단방향 소자이다. 드레인 전류 매개변수, 커패시턴스 매개변수 등 다양한 매개변수를 사용하여 TFET을 모델링할 수 있다.

• 3. Hybrid GAA Characteristics

  MOSFET와 TFET를 함께 사용한 하이브리드 GAA 구조를 모델링했다. MOSFET의 누설 전류가 증가하고 on 전류가 감소하는 문제를 해결할 수 있었다. 또한 TFET의 단방향성, 지연 시간, 전압 천이 구간 문제도 해결할 수 있었다. 이 구조에서 RSNM과 WSNM이 각각 13.741%, 11.04% 향상되었다.

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• 1. MOSFET and TFET

  MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and TFET (Tunnel Field-Effect Transistor) are two distinct types of transistors that have their own advantages and disadvantages. MOSFETs are the most widely used transistors in modern electronics, thanks to their high performance, scalability, and well-established manufacturing processes. However, as device dimensions continue to shrink, MOSFETs face challenges such as increased leakage current and power consumption. TFETs, on the other hand, offer the potential to overcome these limitations by utilizing band-to-band tunneling as the primary mechanism for current flow, which can result in lower subthreshold swing and improved energy efficiency. The TFET structure, with its unique gating mechanism, can also enable better control over the device characteristics and potentially lead to further scaling and integration. While TFETs are still in the research and development stage, their continued advancement and optimization could make them a viable alternative to traditional MOSFETs in certain applications, particularly in low-power and energy-efficient electronics.

• 2. TFET Modeling

  Accurate modeling and simulation of Tunnel Field-Effect Transistors (TFETs) are crucial for the successful design and optimization of these devices. TFET modeling presents several challenges due to the complex physical mechanisms involved, such as band-to-band tunneling, quantum confinement, and interface effects. Researchers have developed various analytical and numerical models to capture the unique characteristics of TFETs, including models based on the Wentzel-Kramers-Brillouin (WKB) approximation, non-equilibrium Green's function (NEGF) formalism, and density functional theory (DFT) calculations. These models aim to accurately describe the current-voltage (I-V) characteristics, subthreshold swing, on-current, and other key performance metrics of TFETs. Ongoing efforts in TFET modeling focus on improving the accuracy and computational efficiency of these models, as well as incorporating the effects of device geometry, material properties, and interface engineering. Robust and reliable TFET models are essential for guiding the design and optimization of these emerging devices, ultimately enabling their successful integration into future low-power and energy-efficient electronic systems.

• 3. Hybrid GAA Characteristics

  Hybrid Gate-All-Around (GAA) transistors, which combine the advantages of different transistor architectures, have gained significant attention in the semiconductor industry as a potential solution to the scaling challenges faced by traditional planar and FinFET devices. The hybrid GAA structure typically integrates multiple gate materials or gate stacks, allowing for enhanced control over the channel and improved device performance. For example, a hybrid GAA transistor may combine a high-k dielectric gate stack with a metal gate for improved electrostatic control, while also incorporating a semiconductor material with a lower effective mass for enhanced carrier transport. The unique characteristics of hybrid GAA transistors, such as their improved subthreshold swing, reduced short-channel effects, and potential for higher on-current, make them an attractive option for future generations of low-power and high-performance integrated circuits. Ongoing research and development in this area focus on optimizing the material selection, gate stack engineering, and device architecture to further enhance the performance and scalability of hybrid GAA transistors. The successful implementation of these advanced transistor structures could pave the way for continued advancements in semiconductor technology and enable the realization of more energy-efficient and high-performance electronic systems.