FPGA를 이용한 IDCT의 co-emulation

소개

Verilog로 하드웨어 및 알고리즘을 설계를 한 후, (IDCT를 수행하는 hardware)
FPGA를 이용하여 co-emulation 하는 과정을 실험하였습니다.

베릴로그 코드는 안의 문서에 들어있습니다.

실험의 주 목적은, 주어진 코드를 최적화 시킴으로써,
hardware의 area(면적)와 delay를 줄이는 데 있습니다. -> 작으면서 빠른 hardware를 위한 최적화

IDCT에 대한..
optimize(최적화) 절차와 결과, 그리고 방법론 등에 대해 기술하였습니다.

앞의 실험 목적과 처음 title 부분들은 영문이지만,
리포트 내용은 모두 한글입니다.

최종 A+ 받은 자료입니다.

목차

1) Synthesize your IDCT design, and if it isn’t synthesizable investigate why and suggest how to fix it
2) Investigate ways to reduce area and improve performance of your IDCT design
A. Survey or propose IDCT hardware architecture which are superior to others with respect to area
and performance (proposing new IDCT hardware architecture is also encouraged)
B. Investigate ways to optimize your IDCT design, e.g., state minimization, redundant logic
elimination, and pipelining, etc

1) Design synthesizable IDCT using Verilog
2) Simulate and verify the design
3) Synthesize the design using ISE
4) Check area and performance report
5) Optimize the area and performance of the hardware by iterating steps from 1) to 4)
6) Verify the operation using co-emulation, i.e., iNCITE

본문내용

1. Purpose
- We designed IDCT hardware and verified the behavior using RTL simulator, i.e., ModelSim, in Exp.
9. To be used as hardware, the RTL design, first, should be synthesized into lower-level, i.e., gate level in ASIC or logic fabric in FPGA. In this experiment, we will experience ways to perform synthesizable RTL design and co-emulation using FPGA board, iNCITE.
- In reality when designing hardware, designers are concerned with not only proper behavior of target hardware but also design constraints, i.e., area, speed, power, etc. The procedure of minimizing area, improving performance, or reducing power consumption is called optimization. In this experiment, we will study and experience optimization method using IDCT hardware.

2. Problem Statement
- Synthesize IDCT design using ISE
- Optimize IDCT hardware which was designed in Exp. 9 (or entirely new design), with respect to
Area (# of slices)
Execution time: (total number of clock cycles until completion) / (Maximum frequency)
Minimize (area) x (execution time) as much as possible

3. Pre Report
1) Synthesize your IDCT design, and if it isn’t synthesizable investigate why and suggest how to fix it.
i) IDCT_2D velilog HDL
다음은 Synthesize 할 IDCT_2D (Inverse Discrete Cosine Transform, 2 dimension) verilog code이다. 생략된 코드로 설명에 필요한 부분만 남겨두었다. IDCT_2D module은 IDCT_1D (Inverse Discrete Cosine Transform, 1 dimension) module 두 개와 Transpose_matrix module로 구성되어 있다. IDCT_2D의 module 연산 순서는 IDCT_1D → Transpose_matrix → IDCT_1D로 되어 있다.
<IDCT_2D verilog code>
module IDCT_2D(clk,rst,start,in0,in1,in2,in3,idct_out0,idct_out1,idct_out2,idct_out3);
input clk, rst, start;
input [15:0] in0, in1, in2, in3;
output [15:0] idct_out0, idct_out1, idct_out2, idct_out3;
<…. 생략…..>
IDCT_1DDUT_IDCT_1D1(.in0(in0),.in1(in1),.in2(in2), .in3(in3),
.out0(out10),.out1(out11),.out2(out12),.out3(out13));

Transpose_matrix DUT_transpose_matrix (.clk(clk),.rst(rst),.start(start),
.trans_in0(out10),.trans_in1(out11),.trans_in2(out12),.trans_in3(out13),
.trans_out0(out20),.trans_out1(out21),.trans_out2(out22),.trans_out3(out23));

IDCT_1D DUT_IDCT_1D2(.in0(out20),.in1(out21),.in2(out22),.in3(out23),
.out0(idct_out0),.out1(idct_out1), .out2(idct_out2),.out3(idct_out3));

Endmodule

// IDCT_1D 모듈 정의
module IDCT_1D(in0,in1,in2,in3,out0,out1,out2,out3);
<…. 생략…..>
endmodule
// counter 모듈 정의
module counter (d, clock, reset, start);
<…. 생략…..>
Endmodule

// Transpose_matrix 모듈 정의
module Transpose_matrix(clk,rst,start, trans_in0,trans_in1,trans_in2,trans_in3, trans_out0,trans_out1,trans_out2,trans_out3);
<…. 생략…..>
endmodule

참고자료

· 없음