Verilog PingPong Game

소개

Verilog를 이용하여 Ping Pong 게임을 구현하였다.
두명의 사용자에 의해 조정되는 조정바1,조정바2
Digital 볼에 의해 게임은 시작된다.
각각의 조정바에 볼이 맞으면 반사되어 상대방으로
튕겨나간다.

컴파일 실행환경

Verilog

본문내용

`timescale 1ns/1ps

module data_gen_TOP(
input clk,
input reset,// active,
output V_sync,H_sync,
input Left_But,Right_But,
output [3:0] VGA_R,VGA_G,VGA_B

/*
output [9:0] H_count,V_count,
output [14:0] addr,
output [2:0] data,

output wr,
output [1:0] sel,
output play
*/
);

wire rst_n=!reset ;
wire active=1`b0;

wire [9:0] H_count,V_count;
wire [14:0]addr;
wire [2:0] data;

wire wr;
wire [1:0] sel;
wire play;


data_gen DUT1
(
clk,rst_n,
V_sync,Left_But,Right_But,
V_count,H_count,
addr,
data
);

wire [7:0] red ={8{data[2]}};
wire [7:0] green={8{data[1]}};
wire [7:0] blue ={8{data[0]}};
wire [7:0] red_o,green_o,blue_o;
wire Digit_on1;
wire Digit_on2;
wire Digit_on3;
wire Digit_on4;
wire Digit_on5;
wire Digit_on6;
wire Digit_on7;
wire Digit_on8;
wire Digit_on9;
wire Digit_on10;

wire Digit_on =Digit_on1 | Digit_on2 | Digit_on3 | Digit_on4 | Digit_on5 | Digit_on6 | Digit_on7 | Digit_on8 | Digit_on9 | Digit_on10;


assign VGA_R=Digit_on? 4`b1111: red_o[3:0];
assign VGA_G=Digit_on? 4`b1111: green_o[3:0];
assign VGA_B=Digit_on? 4`b1111: blue_o[3:0];
/*
assign VGA_R=Digit_on? 4`b1111: red_o[3:0];
assign VGA_G=Digit_on? 4`b0000: green_o[3:0];
assign VGA_B=Digit_on? 4`b0000: blue_o[3:0];
*/
wire [9:0] digit_px5 =10`d472;
wire [9:0] digit_px6 =10`d480;
wire [9:0] digit_px7 =10`d488;
wire [9:0] digit_px8 =10`d496;
wire [9:0] digit_px9 =10`d504;
wire [9:0] digit_px10 =10`d512;

wire [9:0] digit_px1 =10`d520;
wire [9:0] digit_px2 =10`d528;
wire [9:0] digit_px3 =10`d536;
wire [9:0] digit_px4 =10`d544;

wire [9:0] digit_py1 =10`b00_0001_1000;


VGA_controller DUT2
(
clk,
red,green,blue,
red_o,green_o,blue_o,
H_sync,V_sync,
H_count,V_count,
turn_color
);

digit_font DUT7 ( 4`b1010,digit_px5,digit_py1,H_count,V_count,Digit_on5 );
digit_font DUT8 ( 4`b1011,digit_px6,digit_py1,H_count,V_count,Digit_on6 );
digit_font DUT9 ( 4`b0000,digit_px7,digit_py1,H_count,V_count,Digit_on7 );
digit_font DUT10 ( 4`b1100,digit_px8,digit_py1,H_count,V_count,Digit_on8 );
digit_font DUT11 ( 4`b1101,digit_px9,digit_py1,H_count,V_count,Digit_on9 );
digit_font DUT12 ( 4`b1110,digit_px10,digit_py1,H_count,V_count,Digit_on10 );

digit_font DUT3 ( 4`b0001,digit_px1,digit_py1,H_count,V_count,Digit_on1 );
digit_font DUT4 ( 4`b0101,digit_px2,digit_py1,H_count,V_count,Digit_on2 );
digit_font DUT5 ( 4`b0111,digit_px3,digit_py1,H_count,V_count,Digit_on3 );
digit_font DUT6 ( 4`b0000,digit_px4,digit_py1,H_count,V_count,Digit_on4 );

endmodule

참고자료

· 디지털논리,verilog