디지털집적회로 NAND, NOR, XOR gate 설계도 및 DC, Transient 시뮬레이션 결과

목차

1. DC analysis
1) 2-input NAND gate
a. Description of my design
b. Voltage transfer graph for the input combination

2) 2-input NOR gate
a. Description of my design
b. Voltage transfer graph for the input combination

3) 2-input XOR gate
a. Description of my design
b. Voltage transfer graph for the input combination

2. Transient analysis
1) 2-input NAND gate
a. Transient simulation result

2) 2-input NOR gate
a. Transient simulation result

3) 2-input XOR gate
a. Transient simulation result

본문내용

According to the boolean function, pull-down network of NAND gate can be made by connecting two NMOS transistors in series that conduct when both VA and VB are high. By duality, pull-up network consists of two parallel PMOS transistors. The effective pull-up/ pull-down resistance of NAND gate should be equal to the effective resistance of the unit inverter. Because NMOS transistors are connected in series, their effective resistance is doubled, so their size should be twice the size of the unit inverter (WN/LN=4λ/2λ). In case of PMOS, considering the worst case which is that only one of two PMOS is turned on, the size of PMOS should be equal to the unit inverter size (WP/LP=5.734λ/2λ).

There is a large variation between case (1), (2) and (3). This is because in the case (3), both transistors in the pull-up network are on simultaneously for A=B=0, representing a strong pull-up. In the case (1) and (2), only one of the pull-up devices is on,

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