숭실대학교 정통전 디지털공학실험 Quartus 프로젝트 입니다. quartus프로젝트파일, testbench, 보고서, 사진들 다 포함 만점짜리입니다 술자리 Up-Down게임

소개글

숭실대학교 정통전 디지털공학실험 Quartus 프로젝트 입니다. quartus 프로젝트파일, testbench , 보고서, 사진들 다 포함 만점짜리입니다. 술자리 Up-Down게임을 만들었습니다. 어디서 베껴온게 아니라 제가 일일이 다 작성하고 회로그림하고 테스트벤치 파일 전부 들어 있습니다. 이런거 만든 사람 없어서 베꼇다는 그런 말도 안나오고 좋을겁니다.
실험 말고도 디지털공학 과목 프로젝트로 만들어도 괜찮을 듯 합니다.

목차

1. 동작설명
2. 전체 block
3. 상세 block
4. ModelSim 결과파형.분석
5. 보드 동작 사진

본문내용

1. 동작설명

이번 프로젝트로 술게임 중 하나인 Up-Down 게임을 만들어보았다. 기능으로는 벌칙 숫자를 정해놓고 숫자를 하나씩 입력하면서 7segment LED에 나오는 UP과 –- 표시를 보며 벌칙숫자에 접근한다. 벌칙숫자와 입력숫자가 같아진다면 7 segment LED에는 아무런 불이 들어오지 않 으며, 또한 LEDR[0]에 벌칙에 걸렸다는 불이 들어온다.

SW[0~3]은 입력숫자를 정할 수 있으며, SW[4~7]은 벌칙숫자를 정할 수 있다. SW[9]는 en을 값으로 장치의 동작여부를 결정할 수 있다. 결과로는 7segment LED에 각각의 상황에 맞춰서 UP와 –-, 그리고 아 무런 불도 들어오지 않게 된다. 또한 LEDR[0]에는 벌칙에 걸렸을 때 불 이 들어오며, 벌칙이 걸리지 않았을 때는 LEDR[9]에 불이 들어온다.

<중 략>

xnor gate는 값이 같을때만 1을 출력하기 때문에 a와 b값의 각각의 같은 자리수의 값을 xnor로 연결하여 그 결과를 하나의 and게이트로 연결하였다. 그렇게 되면 각 자리의 모든 값이 같을 때 and게이트의 출력이1이 되기 때문에 a와 b값의 동일여부를 판별할 수 있다.
그리고 이 and게이트의 값을 ledred에 연결하여 값이 같을 때 빨간불이들어오며, and게이트의 결과에 not게이트를 연결하여 값이 다를 때는초록불이 들어와서 벌칙이 걸렸을 때 빨간불, 걸리지 않았을 때는 초록불이 들어오게 만들었다. (보드동작시에는 초록불이 없어서 빨간불로 대체함.)

참고 자료

없음

압축파일 내 파일목록

project/sdsda/2323/db/.cmp.kpt
project/sdsda/2323/db/lab1.(0).cnf.cdb
project/sdsda/2323/db/lab1.(0).cnf.hdb
project/sdsda/2323/db/lab1.(1).cnf.cdb
project/sdsda/2323/db/lab1.(1).cnf.hdb
project/sdsda/2323/db/lab1.(2).cnf.cdb
project/sdsda/2323/db/lab1.(2).cnf.hdb
project/sdsda/2323/db/lab1.asm.qmsg
project/sdsda/2323/db/lab1.asm.rdb
project/sdsda/2323/db/lab1.asm_labs.ddb
project/sdsda/2323/db/lab1.cbx.xml
project/sdsda/2323/db/lab1.cmp.bpm
project/sdsda/2323/db/lab1.cmp.cdb
project/sdsda/2323/db/lab1.cmp.hdb
project/sdsda/2323/db/lab1.cmp.idb
project/sdsda/2323/db/lab1.cmp.logdb
project/sdsda/2323/db/lab1.cmp.rdb
project/sdsda/2323/db/lab1.cmp_merge.kpt
project/sdsda/2323/db/lab1.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
project/sdsda/2323/db/lab1.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
project/sdsda/2323/db/lab1.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
project/sdsda/2323/db/lab1.db_info
project/sdsda/2323/db/lab1.eda.qmsg
project/sdsda/2323/db/lab1.fit.qmsg
project/sdsda/2323/db/lab1.hier_info
project/sdsda/2323/db/lab1.hif
project/sdsda/2323/db/lab1.ipinfo
project/sdsda/2323/db/lab1.lpc.html
project/sdsda/2323/db/lab1.lpc.rdb
project/sdsda/2323/db/lab1.lpc.txt
project/sdsda/2323/db/lab1.map.ammdb
project/sdsda/2323/db/lab1.map.bpm
project/sdsda/2323/db/lab1.map.cdb
project/sdsda/2323/db/lab1.map.hdb
project/sdsda/2323/db/lab1.map.kpt
project/sdsda/2323/db/lab1.map.logdb
project/sdsda/2323/db/lab1.map.qmsg
project/sdsda/2323/db/lab1.map.rdb
project/sdsda/2323/db/lab1.map_bb.cdb
project/sdsda/2323/db/lab1.map_bb.hdb
project/sdsda/2323/db/lab1.map_bb.logdb
project/sdsda/2323/db/lab1.pre_map.hdb
project/sdsda/2323/db/lab1.pti_db_list.ddb
project/sdsda/2323/db/lab1.root_partition.map.reg_db.cdb
project/sdsda/2323/db/lab1.routing.rdb
project/sdsda/2323/db/lab1.rtlv.hdb
project/sdsda/2323/db/lab1.rtlv_sg.cdb
project/sdsda/2323/db/lab1.rtlv_sg_swap.cdb
project/sdsda/2323/db/lab1.sgdiff.cdb
project/sdsda/2323/db/lab1.sgdiff.hdb
project/sdsda/2323/db/lab1.sld_design_entry.sci
project/sdsda/2323/db/lab1.sld_design_entry_dsc.sci
project/sdsda/2323/db/lab1.smart_action.txt
project/sdsda/2323/db/lab1.sta.qmsg
project/sdsda/2323/db/lab1.sta.rdb
project/sdsda/2323/db/lab1.sta_cmp.7_slow_1200mv_85c.tdb
project/sdsda/2323/db/lab1.tis_db_list.ddb
project/sdsda/2323/db/lab1.tiscmp.fast_1200mv_0c.ddb
project/sdsda/2323/db/lab1.tiscmp.slow_1200mv_0c.ddb
project/sdsda/2323/db/lab1.tiscmp.slow_1200mv_85c.ddb
project/sdsda/2323/db/lab1.tmw_info
project/sdsda/2323/db/lab1.vpr.ammdb
project/sdsda/2323/db/logic_util_heursitic.dat
project/sdsda/2323/db/prev_cmp_lab1.qmsg
project/sdsda/2323/incremental_db/compiled_partitions/lab1.db_info
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.ammdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.cdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.dfp
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.hdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.logdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.cmp.rcfdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.cdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.dpi
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.hbdb.cdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.hbdb.hb_info
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.hbdb.hdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.hbdb.sig
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.hdb
project/sdsda/2323/incremental_db/compiled_partitions/lab1.root_partition.map.kpt
project/sdsda/2323/incremental_db/README
project/sdsda/2323/output_files/lab1.asm.rpt
project/sdsda/2323/output_files/lab1.done
project/sdsda/2323/output_files/lab1.eda.rpt
project/sdsda/2323/output_files/lab1.fit.rpt
project/sdsda/2323/output_files/lab1.fit.smsg
project/sdsda/2323/output_files/lab1.fit.summary
project/sdsda/2323/output_files/lab1.flow.rpt
project/sdsda/2323/output_files/lab1.jdi
project/sdsda/2323/output_files/lab1.map.rpt
project/sdsda/2323/output_files/lab1.map.summary
project/sdsda/2323/output_files/lab1.pin
project/sdsda/2323/output_files/lab1.sof
project/sdsda/2323/output_files/lab1.sta.rpt
project/sdsda/2323/output_files/lab1.sta.summary
project/sdsda/2323/simulation/modelsim/gate_work/_info
project/sdsda/2323/simulation/modelsim/gate_work/_lib.qdb
project/sdsda/2323/simulation/modelsim/gate_work/_lib1_0.qdb
project/sdsda/2323/simulation/modelsim/gate_work/_lib1_0.qpg
project/sdsda/2323/simulation/modelsim/gate_work/_lib1_0.qtl
project/sdsda/2323/simulation/modelsim/gate_work/_vmake
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_info
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_17.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_17.qpg
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_17.qtl
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_18.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_18.qpg
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_lib1_18.qtl
project/sdsda/2323/simulation/modelsim/verilog_libs/altera_ver/_vmake
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_info
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_16.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_16.qpg
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_16.qtl
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_17.qdb
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_17.qpg
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_lib1_17.qtl
project/sdsda/2323/simulation/modelsim/verilog_libs/cycloneive_ver/_vmake
project/sdsda/2323/simulation/modelsim/lab1.sft
project/sdsda/2323/simulation/modelsim/lab1.vo
project/sdsda/2323/simulation/modelsim/lab1_modelsim.xrf
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak1
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak10
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak11
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak2
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak3
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak4
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak5
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak6
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak7
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak8
project/sdsda/2323/simulation/modelsim/lab1_run_msim_gate_verilog.do.bak9
project/sdsda/2323/simulation/modelsim/modelsim.ini
project/sdsda/2323/simulation/modelsim/msim_transcript
project/sdsda/2323/simulation/modelsim/vsim.wlf
project/sdsda/2323/D_block.bsf
project/sdsda/2323/MUX2x1_block.bsf
project/sdsda/2323/d_latch.bsf
project/sdsda/2323/decoder1_block.bsf
project/sdsda/2323/decoder2_block.bsf
project/sdsda/2323/lab1.bdf
project/sdsda/2323/lab1.qpf
project/sdsda/2323/lab1.qsf
project/sdsda/2323/lab1.qws
project/sdsda/2323/lab1_nativelink_simulation.rpt
project/sdsda/2323_tb/D_block.v
project/sdsda/2323_tb/D_block_tb.v
project/sdsda/2323_tb/D_block_tb.v~
project/sdsda/2323_tb/MUX2x1.v
project/sdsda/2323_tb/MUX2x1.v.bak
project/sdsda/2323_tb/MUX2x1_tb.v
project/sdsda/2323_tb/MUX2x1_tb.v.bak
project/sdsda/2323_tb/d_latch.v
project/sdsda/2323_tb/d_latch_tb.v
project/sdsda/2323_tb/d_latch_tb.v~
project/sdsda/2323_tb/decoder1_block.v
project/sdsda/2323_tb/decoder1_block.v.bak
project/sdsda/2323_tb/decoder2_block.v
project/sdsda/2323_tb/decoder2_block.v.bak
project/sdsda/2323_tb/lab1_tb.v
project/sdsda/2323_tb/lab1_tb.v.bak
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㄱㅗㅊㅏㄹ/demux1x4/DEMUX1x4.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㄱㅗㅊㅏㄹ/demux1x4/DEMUX1x4_tb.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㄱㅗㅊㅏㄹ/mux4x1/MUX4x1.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㄱㅗㅊㅏㄹ/mux4x1/MUX4x1_tb.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㅅㅣㄹㅎㅓㅁㄱㅘㅈㅓㅇ/demux1x2/DEMUX1x2.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㅅㅣㄹㅎㅓㅁㄱㅘㅈㅓㅇ/demux1x2/DEMUX1x2_tb.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㅅㅣㄹㅎㅓㅁㄱㅘㅈㅓㅇ/mux2x1/MUX2x1.v
project/sdsda/project/6ㅈㅜㅊㅏ_ㅅㅣㄹㅎㅓㅁ5__1_57577048_0_15607121245411/ㅅㅣㄹㅎㅓㅁㄱㅘㅈㅓㅇ/mux2x1/MUX2x1_tb.v
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/1.latch/d_latch.v
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/1.latch/d_latch_tb.v
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/1.latch/d_latch_tb.v~
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/2.flipflop/D_block.v
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/2.flipflop/D_block_tb.v
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/2.flipflop/D_block_tb.v~
project/sdsda/project/lab7_latch_flipflop_5_7_1_4436248264464/.DS_Store
project/sdsda/project/.DS_Store
project/sdsda/project/D_block.v
project/sdsda/project/D_block_tb.v
project/sdsda/project/D_block_tb.v~
project/sdsda/project/decoder1_block.v
project/sdsda/project/decoder2_block.v
project/sdsda/project/lab1.bdf
project/sdsda/project/lab12.ipinfo
project/sdsda/project/ㄷㅣㅋㅗㄷㅓ1 ㅌㅔㅅㅡㅌㅡㅂㅔㄴㅊㅣ.txt
project/sdsda/project/ㄷㅣㅋㅗㄷㅓ2 ㅌㅔㅅㅡㅌㅡㅂㅔㄴㅊㅣ.txt
project/sdsda/project/ㅈㅓㄴㅊㅔㅌㅔㅅㅡㅌㅡㅂㅔㄴㅊㅣ.txt
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project/sdsda/.DS_Store
project/.DS_Store
.DS_Store
13ㅈㅜㅊㅏㅍㅡㄹㅗㅈㅔㄱㅌㅡㅂㅗㄱㅗㅅㅓ.pdf
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