ALU의 Structural구조와 Behavioral구조의 비교

목차

1. Structural
2. Behavioral
3. ModelSim

본문내용

Structural

`timescale 1ns / 1ps
module ALU
(
input [31:0] A,B,
input [2:0] control_signal,
output [31:0] Y,
output Cout
);

wire [31:0] Bout ,AND, S, OR;
Mux_2to1 mux0(.B(B), .b(~B), .Cin(control_signal[2]), .Bout(Bout));
Adder add0(.A(A), .B(Bout), .Cin(control_signal[2]), .Cout(Cout), .S(S));
AND_m and0(.A(A), .B(Bout), .AND(AND));
OR_m or0(.A(A), .B(Bout), .OR(OR) );
Mux_4to1 mux1(.AND(AND), .OR(OR), .S(S), .Q((31'b0,S[31])), .cin1(control_signal[1:0]), .Y(Y));

endmodule
module Adder
(
input [31:0] A ,B,
input Cin,
output Cout,
output [31:0] S);
assign {Cout,S} = A+B+Cin;
endmodule

module AND_m(input [31:0] A,B, output [31:0] AND);
assign AND = A&B;
endmodule

module OR_m(input [31:0] A, B, output[31:0] OR);
assign OR = A|B;
endmodule

<이하생략>

참고 자료

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