[공학기술]디지털 시스템 설계 6장 연습문제(일부)

소개글

디지털 시스템 설계6장 연습문제 입니다.PCS(충북대)교수님과목입니다.
VHDL 코드와 웨이브폼 포함

목차

P 6.3 Draw a D latch with enable similar to the circuit in figure 6.6(a), but use NAND gates instead of the multiplexer.
P6.5 Derive the truth table for a negative edge-triggered D flip-flop.
P6.9 Do Problem P6.8 for a JK flip-flop using SR latches.
P6.11 Complete the timing diagram for the circuit in figure P6.11. assume that the signal delay through the NOR gates is 3 ns. and the delay through the NOT gate is 1 ns.

본문내용

P 6.3 Draw a D latch with enable similar to the circuit in figure 6.6(a), but use NAND gates instead of the multiplexer.

본문 회로 참조

참고 자료

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