캡스톤 발표 자료
- 최초 등록일
- 2023.06.22
- 최종 저작일
- 2020.01
- 17페이지/ MS 파워포인트
- 가격 10,000원
소개글
"캡스톤 발표 자료"에 대한 내용입니다.
목차
1. INTRODUCTION
2. MOSFET AND TFET
3. TFET MODELING
4. Hybrid GAA Characteristics
5. Conclusion
본문내용
INTRODUCTION
TFET has emerged as one of the promising candidates for ultralow-power (ULP) applications.
We investigate and express SNM, which is an evaluation element of the SRAM.
And finally, we present hybrid GAA 6T SRAM using TFET and MOSFET together.
참고 자료
STFET-Based Robus 7T SRAM Cell for Low Power Application. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 9, SEPTEMBER 2019
A 32nm Tunnel FET SRAM for Ultra Low Leakage. Institut Superieur d'Electronique de Paris (ISEP)
Design and Analysis of Robust Tunneling FET SRAM. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013
S. Ahmad, N. Alam, and M. Hasan, “Robust TFET SRAM cell for ultralow power IoT applications,” AEU Int. J. Electron. Commun., vol. 89, pp. 70–76, 2018. doi: 10.1016/j.aeue.2018.03.029.
Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS design considerations,” in
D. H. Morris, U. E. Avci, and I. A. Young, “Variation-tolerant dense TFET memory with low Vmin matching low-voltage TFET logic,” in Proc. Symp. VLSI Technol. (VLSI Technol.), Jun. 2015, pp. T24–T25. doi: 10.1109/VLSIT.2015.7223688.