Memory buffer controller 설계

소개글

과목 - ASIC 설계
Verilog 를 이용하여 Memory buffer controller 설계한 것입니다.
NC 와 Simplify 로 검증한 결과입니다.

목차

1. Title
2. Name
3. 설계 베이스
4. Code
5. 결과(NC, Simplify)
* Timing report
6. Reference

본문내용

// define a memory buffer controller
module memory_buffer_controller(clock, reset, read_write, ready, oe, we);

// INPUT
input clock, reset, read_write, ready;

// OUTPUT
output oe, we;

reg oe, we;

// ASSIGN STATEMENTS
parameter [1:0] IDLE = 2`d0,
DECISION = 2`d1,
READ = 2`d2,
WRITE = 2`d3;
reg [1:0] state, next;

always@(posedge clock)
if (~reset)
state <= IDLE;
else
state <= next;

always@(state or read_write or ready)
begin
next = 2`dx;

참고 자료

Logic and computer design fundamentals 3rd ed. – Pearson
Verilog HDL – SAMIR PALNITKAR forward by Prabhu Goel