성균관대학교 디지털집적회로설계 CAD 세번째 과제
- 최초 등록일
- 2020.11.29
- 최종 저작일
- 2019.04
- 11페이지/
어도비 PDF
- 가격 3,000원
* 본 문서는 PDF문서형식으로 복사 및 편집이 불가합니다.
소개글
성균관대학교 디지털집적회로설계 과목 CAD 과제입니다. (학점은 A입니다)
꼭 과제를 위해서가 아니더라도, CAD 실습 과제의 주제가 반도체 쪽 실무적인 관점에서
공부를 하기에 좋은 자료이니 목차 참고하시고 필요하신 내용이 있다면 참고하시면 좋을것 같아요! ^^
목차
1. Create schematic and symbol of TGFF(Transmission Gate Flip-flop), and check the functionality of flip-flop. Attach screenshots of your work.
2. Below figure represents another implementation of D flip-flop, named ACFF(Adaptive Coupling Flip-flop). Create schematic and symbol of ACFF, and check the functionality of flip-flop. Attach screenshots of your work.
3. Measure the set-up time of TGFF and ACFF respectively using method below. Which flip-flop(TGFF or ACFF) is better in terms of set-up time?
4. Measure the average power of TGFF and ACFF respectively over 10 clock cycles using method below.
1) Attach screenshot of waveform of CLK, D, and Q
2) Calculate power using integ(integration) function of “[Tools]-[Calculator]” menu
3) Write your calculation result on report like below table.
4) Write why you should calculate both ① and ②.
5) Compare the value of ① of TGFF and ACFF. Which one is bigger and write the reason you think.
6) Compare the value of ② of TGFF and ACFF. Which one is bigger and write the reason you think.
7) Compare the value of ①+②. Which flip-flop(TGFF or ACFF) is better in terms of power consumption?
5. Create a layout of TGFF and attach a screenshot of your work. (You don’t have to create a layout of ACFF) Refer to layout constraint and attached layout guideline ppt.
6. Run DRC and LVS of the TGFF layout using Assura. Capture your DRC and LVS logs like below and attach it in report.
7. Submit your DRC and LVS log files. (Follow instruction below)
본문내용
<썸네일을 참고해 주세요>
참고 자료
없음
