성균관대학교 디지털집적회로설계 CAD 두번째 과제
- 최초 등록일
- 2020.11.29
- 최종 저작일
- 2019.04
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소개글
성균관대학교 디지털집적회로설계 과목 CAD 과제입니다. (학점은 A입니다)
꼭 과제를 위해서가 아니더라도, CAD 실습 과제의 주제가 반도체 쪽 실무적인 관점에서
공부를 하기에 좋은 자료이니 목차 참고하시고 필요하신 내용이 있다면 참고하시면 좋을것 같아요! ^^
목차
1. Create schematics and symbols of inverter, 2-input NAND gate, 2-input NOR gate, 2-input XOR gate which are standard cells. Verify the functionality of these logic gates you have designed with transient simulation which includes all possible input combinations. Attach screenshots of your work.
2. Create a schematic and symbol of a 2:1 MUX using 3 2-input NAND gates and 1 inverter. Verify the functionality of the 2:1 MUX you have designed with transient simulation which includes all possible input combinations (8cases). Attach screenshots of schematic, symbols and simulation result(waveform).
3. Create layouts for an inverter, a 2-input NAND gate, 2-input NOR gate, 2-input XOR gate. Attach a screenshot of your layout. - Width of VDD/GND lines: 0.2um (Metal1) - Pitch of a cell: 3.08um (distance between the center of VDD line and that of GND line) - Put transistors between VDD and GND line. - Only use metal 1 for routing in a standard cell level except XOR gate. - You can use metal 2, 3 for routing in a XOR gate. Metal 2 and 3 should be orthogonal.(If metal 2 is horizontal, metal 3 should be vertical)
4. Using standard cell layouts, create a layout for the 2:1 MUX. Attach a screenshot of your layout. - Width of VDD/GND lines: 0.2um (Metal1) - Pitch of a cell: 3.08um (distance between the center of VDD line and that of GND line) - Put transistors between VDD and GND line. - You can use metal 2,3 for routing in a 2:1 MUX. Metal 2 and 3 should be orthogonal.(If metal 2 is horizontal, metal 3 should be vertical)
5. Run DRC/LVS of the 2:1 MUX layout using Assura. Capture your DRC/LVS logs like below and attach it in report.
6. Submit your DRC and LVS log files. (follow instruction below)
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