디지털논리회로실험(Verilog HDL) - 8-bit Signed Adder/Substractor, Multiplier

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디지털논리회로실험 레포트

목차

1. 관련이론

2. 실험
2.1 Part Ⅱ : 8-bit Signed Adder/Subtractor(두 개의 8-bit Signed Number를 더하는 회로 설계)
2.2 Part Ⅲ 4-bit Multiplier(16진수 2개를 곱하는 4bit Multiplier. P = A * B)
2.3 Part Ⅵ Sum of Multiplications

본문내용

1. 관련이론
◉ Adders

→ Adds two N-bit binary numbers
-2-bit adder: adds two 2-bit numbers, outputs 3-bit result
-e.g., 01 + 11 = 100 (1 + 3 = 4)

→ Can design using combinational design process of Ch 2, but doesn’t work well for typical N
-Why not?

1) Why Adders Aren’y Built Using Standard Combinational Design Process
⑴ Truth table too big
-2-bit adder’s truth table shown : rows
-8-bit adder : rows
-16-bit adder : ~4 billion rows
-32-bit adder : ...
⑵ Big truth table with numerous 1s/0s yields big logic
-Plot shows number of transistors for N-bit adders, using state-of-the-art automated combinational design tool

< 중 략 >

2. 실험

2.1 Part Ⅱ : 8-bit Signed Adder/Subtractor(두 개의 8-bit Signed Number를 더하는 회로 설계)

(1) Summary

It can perform both addition and subtraction of eight-bit numbers. Use switch to specify whether addition or subtraction should be performed.

*조건

- SW15-8, SW7-0으로 2개의 8bit 입력을 받는다.
- SW15,SW7은 부호를 의미한다.(1은 음수, 0은 양수)

참고 자료

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