논리회로설계실험_4조_실험일(080506)_보고서
- 최초 등록일
- 2011.11.19
- 최종 저작일
- 2008.05
- 5페이지/ 한컴오피스
- 가격 1,000원
소개글
논리회로설계실험
목차
없음
본문내용
Counter
HDL Code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
clk_out : out STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behave of counter is
signal tmp_clk_cnt : std_logic_vector(2 downto 0);
signal tmp_q : std_logic_vector(3 downto 0);
signal tmp_clk_out: std_logic;
begin
process(clk,rst)
begin
if (rst = `0`) then
tmp_clk_cnt <= "000";
tmp_clk_out <= `0`;
elsif (clk` event and clk=`1`) then
if (tmp_clk_cnt="100") then
tmp_clk_cnt <= "000";
tmp_clk_out<= not tmp_clk_out;
else
tmp_clk_cnt <= tmp_clk_cnt + 1;
end if;
else
tmp_clk_out<=tmp_clk_out;
end if;
end process;
clk_out<=tmp_clk_out;
process(clk,rst)
begin
if(rst=`0`) then
q<= (others=>`0`);
tmp_q<=(others=>`0`);
elsif(clk` event and clk=`1`) then
tmp_q<=tmp_q+1;
q<=tmp_q;
else
tmp_q<=tmp_q;
end if;
end process;
end Behave;
참고 자료
없음