flip-flop and counter design(예비)

소개글

flip-flop and counter design(예비)

목차

1. Objective

2. Theory

(1) Latch / Flip-Flop

(2) Shift Register

(3) Counter

(4) Up / Down / Preset Counter

3. Reference

본문내용

(4) Up / Down / Preset Counter
Counter is a circuit utilizing basic flip-flop devices to count numbers every clock period. There are asynchronous method in which only the LSB part is triggered by the clock, and the other flip-flops are triggered by its previous flip-flop, and the synchronous method where all the flip-flops are triggered by the clock and the next value is decided by each logic circuit. In experiment, synchronous method is used. Counter can be divided into up-counters and down-counters by its counting direction. In up-counter, the number increases with the clock, and in down-counter, it decreases. Preset-able counter can let the user decide the starting value in up-counter and operate accordingly. The counter has been synchronized by clock signals, while up/down inputs are placed so that up-down counter operations can be
performed, and when PL is `0`, counter resets to the values of P0, P1, P2, and P3. Counter operation starts from the reset values, P0, P1, P2, P3.

참고 자료

- Contemporary Logic Design ( 2th Edition ), Randy H.Katz
- Wikipedia dictionary
- Naver 백과사전
- Fundamental of Logic Design ( 5th Edition ), Charles H. Roth jr
- http://www.eelab.usyd.edu.au/digital_tutorial/part2/register05.html)