전기전자기초실험 Arithmetic Circuit Design 결과보고서

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연세대학교 전기전자기초실험 9장 보고서(영문)
다른 chapter는 제 박스에서 검색해주세요.
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목차

- Objective
- Procedure
1. 4-bit adder/subtracter
2. 4-bit ALU
- Logic operation (M=1, Cin=0)
- Arithmetic Operation (M=0, Cin=0)
- The Code
- Report
1. Survey the strength/weakness of carry look ahead method and compare it with the circuit above.
2. Find the maximum delay route of 4-bit adder/subtracter, then calculate the maximum operating frequency when this circuit is run by clock.
3. Survey other types of adder, then find the fastest one for 32-bit adding operation.
4. If you have troubled in compiling because of errors after setting input/output pin to FPGA I/O with MAX+Plus Ⅱ > Floorplan Editor, discuss possible reasons.
5. Discuss the reason of time delay(time from input to output) measured by MAX+Plus Ⅱ > Timing Analyzer. If we use clock to design the circuit, find out the maximum operating frequency, and explain why.
6. Design 16-bit ALU with four 4-bit ALU and discuss its time delay measured by MAX+Plus Ⅱ > Timing Analyzer.
- Reference

본문내용

- Objective : Understand the expression of negative binary number and 4-bit adder/subtracter with verilog simulation and FPGA Kit. Based on what we`ve learned before, make ALU(Arithmetic calculation. Then verify this with simulation and FPGA Kit)

- Procedure
1. 4-bit adder/subtracter
`SEL` clock is the a mark of arithmetic design. We assign the `SEL` to number `0`. As we pictured on the report, it is easily confirmed that pushing the `0` button means `-`. That`s why S=3 when A=0100, B=0001 in the picture of page 1 Waveform of 4-bit adder/subtracter. Followed picture means -8-2=-10 (with overflow). The overflow can be checked the 6th diode which turns on in the picture(Because it is out of range of expression). A assigns the `1234`, B assigns the `ABCD`. In the picture 0, 1, C pushed by operator. SO A = 1000, B = 0010, SEL=1.

As I mentioned before when out of arithmetic range happens, overflow will be 1. Followed table showed that as the example of 7+4=11 which has the overflow 1. The other case doesn`t have the overflow value. Add/Subtract mark depend on SEL.

참고 자료

♣ Electric Circuit Experiment : Logic Circuit
♣ Contemporary Logic Design 2nd Edition (Randy H. Katz)