[VHDL]64point FFT/IFFT VHDL 구현 소스코드

소개글

64point FFT/IFFT 동작을 VHDL로 구현한 소스코드입니다.
졸업작품이나, 프로젝트에 도움이 되길 바랍니다.

목차

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본문내용

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY delay IS
GENERIC(N_DLY : INTEGER := 32;
N_BIT : INTEGER := 10);
PORT( rstn : IN STD_LOGIC;
clk : IN STD_LOGIC;
xi_in : IN SIGNED(N_BIT-1 DOWNTO 0);
xq_in : IN SIGNED(N_BIT-1 DOWNTO 0);
yi_out : OUT SIGNED(N_BIT-1 DOWNTO 0);
yq_out : OUT SIGNED(N_BIT-1 DOWNTO 0));
END;

ARCHITECTURE be OF delay IS

TYPE table_signed IS ARRAY (NATURAL RANGE <>) OF SIGNED(N_BIT-1 DOWNTO 0);
SIGNAL xi_reg : table_signed(0 TO N_DLY-1);
SIGNAL xq_reg : table_signed(0 TO N_DLY-1);

BEGIN

PROCESS(rstn, clk)
BEGIN
IF rstn = `0` THEN
FOR i IN 0 TO N_DLY-1 LOOP
xi_reg(i) <= (OTHERS => `0`);
xq_reg(i) <= (OTHERS => `0`);
END LOOP;
ELSIF clk`EVENT AND clk = `1` THEN
xi_reg <= xi_in & xi_reg(0 TO N_DLY-2);
xq_reg <= xq_in & xq_reg(0 TO N_DLY-2);
END IF;
END PROCESS;

yi_out <= xi_reg(N_DLY-1);
yq_out <= xq_reg(N_DLY-1);

END;

참고 자료

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