VHDL - 4_8 Ram, 4_8 Rom, fifo, lifo
- 최초 등록일
- 2006.11.04
- 최종 저작일
- 2004.07
- 7페이지/
한컴오피스
- 가격 1,000원
소개글
4_8 Ram,
4_8 Rom,
FIFO(선입선출법 :First In First Out),
LIFO(선입선출법 :Last In First Out)
VHDL 소스 코드
컴파일 실행환경
MAXPLUS II V10.2
본문내용
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity conram48 is
generic(Dsize : positive := 8 ;
Asize : positive := 4);
port(ADDRESS : in std_logic_vector(Asize-1 downto 0);
DIN : in std_logic_vector(Dsize-1 downto 0);
RAM_EN : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
DO : out std_logic_vector(Dsize-1 downto 0));
end ;
architecture OPERATION of conram48 is
constant Aword : positive := 2**asize;
SIGNAL word : std_logic_vector(2**asize-1 downto 0);
type MEMORY is array (0 to Aword-1) of std_logic_vector(Dsize-1 downto 0);
signal RAM_TBL : MEMORY;
begin
decoder:PROCESS(address)
BEGIN
word <= "0000000000000000";
IF address = "0000" THEN
word(0) <=`1`;
elsif address = "0001" THEN
word(1) <=`1`;
elsif address = "0010" THEN
word(2) <=`1`;
elsif address = "0011" THEN
word(3) <=`1`;
elsif address = "0100" THEN
word(4) <=`1`;
elsif address = "0101" THEN
word(5) <=`1`;
elsif address = "0110" THEN
word(6) <=`1`;
elsif address = "0111" THEN
word(7) <=`1`;
elsif address = "1000" THEN
word(8) <=`1`;
elsif address = "1001" THEN
word(9) <=`1`;
elsif address = "1010" THEN
word(10) <=`1`;
elsif address = "1011" THEN
word(11) <=`1`;
elsif address = "1100" THEN
word(12) <=`1`;
elsif address = "1101" THEN
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