연세대학교 기초디지털실험 8주차 결과레포트
- 최초 등록일
- 2022.04.18
- 최종 저작일
- 2020.11
- 24페이지/ 어도비 PDF
- 가격 5,000원
목차
Ⅰ. Theory
Ⅱ. code explanation
Ⅲ. Result & discussion
Ⅳ. Plus : HSIZE
Ⅴ. Reference
본문내용
1. AXI4
AXI stands for Advanced extended interface. AXI is a multi-channel bus that is optimized for reading and writing. The AXI protocol was first published in 2003 as part of the AMBA 3 protocol to compensate for the shortcomings of the AHB protocol that was first announced and to reflect the changing chip design environment, and continuous updates have been made with successive announcements of AMBA4 in 2010 and AMBA5 in 2013. The AXI protocol for each version of AMBA is named AXI3, AXI4, AXI5, etc. after the name of the AMBA.
The main features of AXI are as follows: The master and the slave are connected by five channels, where the master and slave transmit data through the read address channel and the read data channel, rather than unilaterally output addresses or data from the master in the read operation. AXI can use register slices to design bus timing without lowering the operating frequency of the entire bus.
참고 자료
Yonsei univ. Electrical Electronic Engineering - Week 8 Lecture