디지털논리회로실험(Verilog HDL) - Real-time clock, counter
- 최초 등록일
- 2019.08.29
- 최종 저작일
- 2017.11
- 8페이지/
한컴오피스
- 가격 1,000원
소개글
디지털논리회로실험 레포트
목차
1. 관련이론
2. 실험
2.1 Part Ⅱ: Real-time Clock
2.3 Part Ⅳ : M-digit base-N Up/Down Counter
본문내용
1. 관련이론
◉ Measuring Time Between Events using an Up-Counter
⓵ Initially clear to 0. event : set cnt=1. event : set cnt=0.
-Then, multiply counted clock cycles by clock period to determine time.
⓶ Ex : Highway speed measurement system
-Two sensors “a” and “b” in road
-Use FSM to detect “a” becoming 1, set cnt=1. set cnt=0 when “b”=1
-If clock is 1 kHz(period is 1ms), then time is C * 0.001s
< 중 략 >
2.3 Part Ⅳ : M-digit base-N Up/Down Counter
Implement a M-digit base-N up/down counter. Display the contents of the counter on the 7-segment displays, HEXM-1. Derive a control signal, from the 50-MHz clock signal provided on the DE2-115 board, to increment or to decrement the contents of the counter at one-second intervals. Use the button switch KEY0 to toggle the up/down behaviors of the counters, and KEY1 to reset the counter to 0.
◉ 시간이 증가/감소하는 카운터
*조건
⓵ HEX1-0에 0-99까지 표시하는 카운터를 설계한다.
⓶ 기본적으로 0에서 시작한다.
⓷ SW0이 1일 때 0.1초당 1씩 증가한다(99에서 더 이상 증가하지 않는다)
참고 자료
없음
