디지털논리회로실험(Verilog HDL) -BCD counter, HEELO shifter

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디지털논리회로실험 레포트

목차

1.관련이론

2.실험
2.1 Part Ⅳ : BCD 카운터 설계
2.2 Part Ⅴ : HELLO Shifter 설계

본문내용

1.관련이론

◉ Blocking Assignment(=)
-계산과 동시에 저장이 이루어진다.
◉ Non-Blocking Assignment(<=)
-선 계산, 후 저장으로 동작함
◉ Blocking vs. Non-blocking Assignments

◉50-MHz clock
- 1초를 카운트 하기 위해 50000000번 카운트 해야한다.
- 50000000을 저장하기 위해 26bit가 필요함
- 50,000[Hz]*1,000[ms] = 50,000,000

◉Behavioral Verilog
⓵ Initial
-Behavior block operates ONCE
-Starts at time 0 (beginning of operation)
-Useful for testbenches
-Can sometimes provide initialization of memories/FFs
-Inappropriate for combinational logic
-Usually cannot be synthesized

⓶ Always
-Behavioral block operates CONTINUOUSLY
-Can use a trigger list to control operation

⓷Trigger list
-Conditionally “execute” inside of always block

< 중 략 >

2.실험

2.1 Part Ⅳ : BCD 카운터 설계

◉실험목적 : 50-MHz clock을 사용하여 counter를 구현해본다.

(1) Summary

Design and implement a circuit that successively flashes digits 0 through 9 on the 7-segment display HEX0. Each digit should be displayed for about one second. Use a counter to determine the one second intervals.

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