ARITHMETIC AND LOGIC UNIT DESIGN

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1bit full adder, Sign-Magnitude Adder/Subtracto, 3-bit arithmetic circuit for 2`s complement represented numbers 를 verilog로 구현한 source code와 test bench code입니다.

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ARITHMETIC AND LOGIC UNIT DESIGN
LAB 5 :
1bit full adder
/
//Source Code
module oneibt(a,b,cin,s,cout
);
input a,b,cin;
output s,cout;
wire r1,r4,r3;

xor (s,r1,cin);
and (r4,a,b);
xor (r1,a,b);
and (r3,cin,r1);
or (cout, r3,r4);

endmodule
//Test Bench
module tb1;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire s;
wire cout;
// Instantiate the Unit Under Test (UUT)
oneibt uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 1;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
cin = 0;
// Wait 100 ns for global reset to finish

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