◈NAND2 Layout -Distance between all input and output pins: 0.58um -Height of entire AOI22: 11.450 um ... -Length of entire AOI22: 1.480 um -Simulation waveform for worst case rise/fall delay(NAND) The input
NAND layout VDD GND Input A Input B Output NAND simulation 3-Input NAND schematic layout NOR schematic ... NAND - NOR gate NAND – NOR gate 의 정의 nMOS , pMOS switch 3 개의 단자로 구성 G : Gate(Control) S : Source(Out) ... 인가 On Off Off On 1 1 출력 1 NAND gate A B Out 0 0 0 1 1 0 1 1 1 인가 0 인가 Off On On Off 1 1 1 출력 1 NAND