연세대 전기전자 기초실험 09년도 레포트 결과 8 Basic Logic Circuit Design
- 최초 등록일
- 2009.12.17
- 최종 저작일
- 2009.05
- 5페이지/ 한컴오피스
- 가격 1,000원
소개글
연세대학교 전기전자 기초실험 09년도 A+ 레포트
목차
1. experiment result
2. Result report
3. 토의 사항
본문내용
there are some hazard at output Y (00->01, 01->10, 10->11, 11->00)
in mux waveform. this caused by time delay.
For example, switch 11 is signal which make flows I2 and switch 00 is signal which make flows I3. When we switch 11->00, signal changes a few times later.
When we assign input/output pins to FPGA, its arrangement was different to our code. So we changed arrangement [3:0] to [0:3] at input, and it operated correctly.
2. Result report
① Using 2×1 multiplexer and 4×1 multiplexer, design 8×1 multiplexer and verify its behavior
we made 8×1 multiplexer consists to two 4x1 mux and one 2x1 mux.
4x1 mux code was in the textbook and we could make 2x1 mux by application this. Next is 8x1 multiplexer verilog HDL code.
참고 자료
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