컴퓨터 구조 과제 4 - 소프트웨어학과

소개글

chapter 13,14,15

목차

1. Instruction size: 3 bytes, byte addressable, Integer: 8bit twos complement representation
R1 = 70, R2= 80, M[70] = 70, M[71] = 71,M[72] = 72
300:MOVR2, #70; R2 <= 70
303:SUBR2, 1@R1; R2 <= R2 - M[R1+1]
306:JP$-9; branch if positive (branch to -9@PC)
1) After executing MOV and SUB instructions, what value is stored in register R2?

2) Show the values of flags (C, Z, S, OV) after SUB instruction.

3) What is the address of the instruction executed after JP instruction?


4) Considering above program, design instruction format with 14 different operations and 13 registers. Determine instruction format, size of OP-code, number and size of operands, etc.



2. A processor does not provide indirect addressing. Assume that the address of an operand is in main memory. How would you access the operand?



3. A pipelined processor has a clock rate of 10GHz and executes a program with 10 million instructions. The pipeline has five stages and instructions are issued at a rate of one per clock.
a)What is the speedup of this processor for this program compared to a non-pipelined processor.
b)What is the MIPS rate for the pipelined and non-pipelined processor.
c)List three pipeline hazards and briefly explain how these hazards affect the performance.

4. Explain the typical distinguishing characteristics common to RISC organization.

5. What is the difference between the superscalar and super-pipelined approaches?

6. Explain the purpose and contents of the interrupt vector table.

7. Explain the difference of the instruction format between x86 processors and ARM processors


8. Show the representation of the following data
1) character ‘2’, 2) integer 2, and 3) real number(single precision) 2.0.

본문내용

19년도 2학기 4번째 과제입니다. 매년 내는 문제 내용은 비슷합니다.

참고 자료

없음