[asic] vhdl을 이용한 시계 설계

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본문내용

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DATE is
port (CLK : in std_logic;
MODE1 : in std_logic_vector (1 downto 0);
MODE2 : in std_logic_vector (1 downto 0);
INCREASE : in std_logic;
HUR_CARRY : in std_logic;
MON : out std_logic_vector (3 downto 0);
DAY : out std_logic_vector (4 downto 0));
end DATE;

architecture A_DATE of DATE is
signal INC_DAY : std_logic;
signal INC_MON : std_logic;
signal MONTH : std_logic_vector (4 downto 0) := "11111";
constant MON_28 : std_logic_vector (4 downto 0) := "11100";
constant MON_30 : std_logic_vector (4 downto 0) := "11110";
constant MON_31 : std_logic_vector (4

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