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"[전자전기컴퓨터설계실험2] Verilog를 이용한 디지털 시계 (알람, 스탑워치, LED 기능 포함)"에 대한 내용입니다.
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본문내용
//Digital_Clock.v
module Digital_Clock(RESETN, CLK, LCD_E, LCD_RS, LCD_RW, LCD_DATA, PIEZO, BUS, BUT, LED);
input RESETN, CLK;
input [7:0] BUS; // BUS_SWITCH
input [15:0] BUT; // BUTTON_SWITCH
output LCD_E, LCD_RS, LCD_RW, PIEZO;
output [7:0] LCD_DATA, LED;
wire LCD_E, PIEZO;
reg LCD_RS, LCD_RW;
reg [2:0] STATE;
reg [7:0] LCD_DATA, LED;
reg [6:0] CNT_CYCLE, CNT_H10, CNT_H1, CNT_M10, CNT_M1, CNT_S10, CNT_S1, CNT_MS10, CNT_MS1; // Registers for default time
reg [6:0] SET_H10, SET_H1, SET_M10, SET_M1; // Register for time setting
reg [6:0] STOP_M10, STOP_M1, STOP_S10, STOP_S1, STOP_MS10, STOP_MS1; // Registers for STOPWATCH
reg [6:0] ALARM_H10, ALARM_H1, ALARM_M10, ALARM_M1; // Registers for ALARM
parameter DELAY = 4'b0000, FUNCTION_SET = 4'b0001, ENTRY_MODE = 4'b0010, DISP_ONOFF = 4'b0011,
LINE1 = 4'b0100, LINE2 = 4'b0101, DELAY_T = 4'b0110, CLEAR_DISP = 4'b0111;
integer CNT, CNT_M;
reg CLK_M;
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