VHDL VLSI SOC 설계step motor
- 최초 등록일
- 2018.11.18
- 최종 저작일
- 2018.01
- 11페이지/ 한컴오피스
- 가격 1,000원
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본문내용
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity motor1_rot is port
(
CLK_4M : IN std_logic;
RSTB : IN std_logic;
MTL_A : OUT std_logic;
MTL_B : OUT std_logic;
MTL_nA : OUT std_logic;
MTL_nB : OUT std_logic
);
end motor1_rot;
architecture RoV_Lab of motor1_rot is
signal cnt : std_logic_vector (15 downto 0);
signal clk_40 : std_logic;
signal mot_cnt : std_logic_vector (1 downto 0);
signal phase_out : std_logic_vector (3 downto 0);
signal stop : std_logic;
signal step_cnt : integer range 0 to 200;
begin
process(RSTB,CLK_4M,cnt)
begin
if RSTB = '0' then
cnt <= (others => '0');
clk_40 <= '0';
elsif rising_edge (CLK_4M) then
if cnt = X"0002" then -- 시뮬레이션시
cnt <= (others => '0');
clk_40 <= not clk_40;
else
cnt <= cnt + 1;
end if;
end if;
end process;
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