VHDL VLSI SOC 설계 doorlock
- 최초 등록일
- 2018.11.18
- 최종 저작일
- 2018.01
- 8페이지/ 한컴오피스
- 가격 1,000원
목차
1. door_lock
2. test banch
본문내용
1. door_lock
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity door_lock is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ps_start : in STD_LOGIC;
ps_end : in STD_LOGIC;
ps_num : in STD_LOGIC_VECTOR (3 downto 0);
door_Open : out STD_LOGIC;
state_out : out STD_LOGIC_VECTOR (4 downto 0)
);
end door_lock;
architecture Behavioral of door_lock is
type states is (ready, in_start, in_end, door_con, end_state);
signal state : states;
signal password : std_logic_vector(3 downto 0):="1001";
signal ps_in : std_logic_vector(3 downto 0);
signal ps_true : std_logic;
signal open_sig : std_logic;
signal lock_sig : std_logic;
signal lock_cnt : std_logic_vector(3 downto 0);
signal cnt_1hz : std_logic_vector(27 downto 0);
signal clk_1hz : std_logic;
begin
process(RST, CLK)
begin
if RST = '0' then
state <= ready;
elsif rising_edge(CLK) then
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