halfadd, fulladd, mux, ALU

소개글

Verilog 입니다.
통째로 다 올렸으니 압축풀고 열으시면 됩니다.~ .

컴파일 실행환경

modelsim

압축파일 내 파일목록

alu_1.v
alu_1.v.bak
alu_1_assign.v
alu_1_assign.v.bak
alu_4.v
alu_4.v.bak
alu_4_assign.v
alu_4_assign.v.bak
and_gate.v
and_gate.v.bak
full_add.cr.mti
full_add.mpf
full_add.v
half_add.v
HomeW.cr.mti
HomeW.mpf
HomeW.v
mux_4_to_1.v
mux_4_to_1.v.bak
or_gate.v
tb_alu_1.v
tb_alu_1.v.bak
tb_alu_1_assign.v
tb_alu_1_assign.v.bak
tb_alu_4.v
tb_alu_4.v.bak
tb_alu_4_assign.v
tb_alu_4_assign.v.bak
tb_and_gate.v
tb_full_add.v
tb_half_add.v
tb_HomeW.v
tb_mux_4_to_1.v
tb_mux_4_to_1.v.bak
tb_or_gate.v
vish_stacktrace.vstf
vsim.wlf
work.zip
work/_info
work/_vmake
work/alu_1/verilog.prw
work/alu_1/verilog.psm
work/alu_1/_primary.dat
work/alu_1/_primary.dbs
work/alu_1/_primary.vhd
work/alu_1_assign/verilog.prw
work/alu_1_assign/verilog.psm
work/alu_1_assign/_primary.dat
work/alu_1_assign/_primary.dbs
work/alu_1_assign/_primary.vhd
work/alu_4/verilog.prw
work/alu_4/verilog.psm
work/alu_4/_primary.dat
work/alu_4/_primary.dbs
work/alu_4/_primary.vhd
work/alu_4_assign/verilog.prw
work/alu_4_assign/verilog.psm
work/alu_4_assign/_primary.dat
work/alu_4_assign/_primary.dbs
work/alu_4_assign/_primary.vhd
work/and_gate/verilog.prw
work/and_gate/verilog.psm
work/and_gate/_primary.dat
work/and_gate/_primary.dbs
work/and_gate/_primary.vhd
work/full_add/verilog.prw
work/full_add/verilog.psm
work/full_add/_primary.dat
work/full_add/_primary.dbs
work/full_add/_primary.vhd
work/half_add/verilog.prw
work/half_add/verilog.psm
work/half_add/_primary.dat
work/half_add/_primary.dbs
work/half_add/_primary.vhd
work/mux_4_to_1/verilog.prw
work/mux_4_to_1/verilog.psm
work/mux_4_to_1/_primary.dat
work/mux_4_to_1/_primary.dbs
work/mux_4_to_1/_primary.vhd
work/or_gate/verilog.prw
work/or_gate/verilog.psm
work/or_gate/_primary.dat
work/or_gate/_primary.dbs
work/or_gate/_primary.vhd
work/tb_alu_1/verilog.prw
work/tb_alu_1/verilog.psm
work/tb_alu_1/_primary.dat
work/tb_alu_1/_primary.dbs
work/tb_alu_1/_primary.vhd
work/tb_alu_1_assign/verilog.prw
work/tb_alu_1_assign/verilog.psm
work/tb_alu_1_assign/_primary.dat
work/tb_alu_1_assign/_primary.dbs
work/tb_alu_1_assign/_primary.vhd
work/tb_alu_4/verilog.prw
work/tb_alu_4/verilog.psm
work/tb_alu_4/_primary.dat
work/tb_alu_4/_primary.dbs
work/tb_alu_4/_primary.vhd
work/tb_alu_4_assign/verilog.prw
work/tb_alu_4_assign/verilog.psm
work/tb_alu_4_assign/_primary.dat
work/tb_alu_4_assign/_primary.dbs
work/tb_alu_4_assign/_primary.vhd
work/tb_and_gate/verilog.prw
work/tb_and_gate/verilog.psm
work/tb_and_gate/_primary.dat
work/tb_and_gate/_primary.dbs
work/tb_and_gate/_primary.vhd
work/tb_full_add/verilog.prw
work/tb_full_add/verilog.psm
work/tb_full_add/_primary.dat
work/tb_full_add/_primary.dbs
work/tb_full_add/_primary.vhd
work/tb_half_add/verilog.prw
work/tb_half_add/verilog.psm
work/tb_half_add/_primary.dat
work/tb_half_add/_primary.dbs
work/tb_half_add/_primary.vhd
work/tb_mux_4_to_1/verilog.prw
work/tb_mux_4_to_1/verilog.psm
work/tb_mux_4_to_1/_primary.dat
work/tb_mux_4_to_1/_primary.dbs
work/tb_mux_4_to_1/_primary.vhd
work/tb_or_gate/verilog.prw
work/tb_or_gate/verilog.psm
work/tb_or_gate/_primary.dat
work/tb_or_gate/_primary.dbs
work/tb_or_gate/_primary.vhd
work/_temp/vlog4s81wx
work/_temp/vlog50znrc
work/_temp/vlog6adbt9
work/_temp/vlog6bh6wc
work/_temp/vlog7rwxdh
work/_temp/vlog8nzgjq
work/_temp/vloga3st64
work/_temp/vlogaggn0w
work/_temp/vlogbkmn4j
work/_temp/vlogbvcz1y
work/_temp/vlogc6rrmz
work/_temp/vlogc8tdyg
work/_temp/vlogctjv04
work/_temp/vlogfftawb
work/_temp/vlogfvkyri
work/_temp/vloghn2hyr
work/_temp/vlogi9n373
work/_temp/vlogjz2sbw
work/_temp/vlogk0vy3d
work/_temp/vlogmtief3
work/_temp/vlogn1a85k
work/_temp/vlognk98k9
work/_temp/vlogq3aiq0
work/_temp/vlogqmv8zf
work/_temp/vlogs0bkek
work/_temp/vlogs6js1h
work/_temp/vlogsqgqr7
work/_temp/vlogwrrv5t
work/_temp/vlogwtd38v
work/_temp/vlogy2xxwr
work/_temp/vlogz4kdkg

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