Pt 나노입자가 분산된 SiO2 박막의 저항-정전용량 관계
(주)코리아스칼라
- 최초 등록일
- 2016.04.02
- 최종 저작일
- 2015.09
- 6페이지/ 어도비 PDF
- 가격 4,000원
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서지정보
ㆍ발행기관 : 한국재료학회
ㆍ수록지정보 : 한국재료학회지 / 25권 / 9호
ㆍ저자명 : 최병준
영어 초록
Resistance switching memory cells were fabricated using atomically dispersed Pt-SiO2 thin film prepared via RF co-sputtering. The memory cell can switch between a low-resistance-state and a high-resistance-state reversibly and reproducibly through applying alternate voltage polarities. Percolated conducting paths are the origin of the low-resistance-state, while trapping electrons in the negative U-center in the Pt-SiO2 interface cause the high-resistance-state. Intermediate resistance-states are obtained through controlling the compliance current, which can be applied to multi-level operation for high memory density. It is found that the resistance value is related to the capacitance of the memory cell: a 265-fold increase in resistance induces a 2.68-fold increase in capacitance. The exponential growth model of the conducting paths can explain the quantitative relationship of resistance-capacitance. The model states that the conducting path generated in the early stage requires a larger area than that generated in the last stage, which results in a larger decrease in the capacitance.
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