[vhdl] VHDL 계산기2

목차

1.키입력처리1,2,3,4

본문내용

VHDL 계산기 키입력 처리 부분 코딩

키입력처리1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity key is
port( clk : in std_logic;
key_0,key_1,key_2,key_3,key_4,key_5,key_6,key_7,key_8,key_9 : in std_logic;
key_a,key_b,key_c,key_d,key_e,key_f : in std_logic;
x1,x2,x3 : buffer integer range 0 to 9;
y1,y2,y3 : buffer integer range 0 to 9;
data : buffer integer range 0 to 9;
count : buffer integer range 0 to 9;
key_event : buffer std_logic;
start : buffer std_logic;
sel : buffer std_logic_vector(1 downto 0));
end key;

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