메모리설계

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메모리설계,VHDL설계실험

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본문내용

RAM
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ram is
port(
CE, RD, WR : in std_logic;
ADDR, IN_DATA : in std_logic_vector(3 downto 0);
OUT_DATA : out std_logic_vector(3 downto 0) :=(others=>`0`)
);
end ram;

architecture behave of ram is

type RAM_WORD is array (0 to 15) of std_logic_vector(3 downto 0);
signal RAM_DATA : RAM_WORD := ("0000", "0000", "0000", "0000",
"0000", "0000", "0000", "0000",
"0000", "0000", "0000", "0000",
"0000", "0000", "0000", "0000");

begin
process(CE, RD, WR, ADDR, IN_DATA)
begin
if (CE=`0`) then
if (WR=`0`) then
RAM_DATA(conv_integer(ADDR))<=IN_DATA;
elsif (WR=`1` and RD=`0`) then
OUT_DATA<=RAM_DATA(conv_integer(ADDR));
end if;
end if;
end process;
end behave;

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