vhdl소스(counter외 20가지)

목차

*vhdㅣ설계
1.2입력and
2.2입력nand
3.full adder
4.mux
.
.

본문내용

******* Latch ********
library IEEE;
use IEEE.std_logic_1164.all;

entity latch11 is
port (
d: in STD_LOGIC;
en: in STD_LOGIC;
q: out STD_LOGIC
);
end latch11;

architecture latch11_behav of latch11 is
begin
process(d,en)
begin
if en='1' then
q <= d;
end if;
end process;
end latch11_behav;

참고 자료

없음